Datasheet

Electrical Characteristics
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor 35
2.10 I
2
C Input/Output Timing Specifications
Table 30 lists specifications for the I
2
C input timing parameters shown in Figure 7.
Table 31 lists specifications for the I
2
C output timing parameters shown in Figure 7.
Table 30. I
2
C Input Timing Specifications between I2C_SCL and I2C_SDA
Num Characteristic Min Max Units
11 Start condition hold time 2 × t
CYC
—ns
I2 Clock low period 8 × t
CYC
—ns
I3 SCL/SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) — 1 ms
I4 Data hold time 0 — ns
I5 SCL/SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 1 ms
I6 Clock high time 4 × t
CYC
—ns
I7 Data setup time 0 — ns
I8 Start condition setup time (for repeated start condition only) 2 × t
CYC
—ns
I9 Stop condition setup time 2 × t
CYC
—ns
Table 31. I
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
Num Characteristic Min Max Units
11
1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Tab l e 31. The I
2
C
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Ta bl e 3 1 are minimum values.
Start condition hold time 6 × t
CYC
—ns
I2
1
Clock low period 10 × t
CYC
—ns
I3
2
2
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
I2C_SCL/I2C_SDA rise time
(V
IL
= 0.5 V to V
IH
= 2.4 V)
——µs
I4
1
Data hold time 7 × t
CYC
—ns
I5
3
3
Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time
(V
IH
= 2.4 V to V
IL
= 0.5 V)
—3ns
I6
1
Clock high time 10 × t
CYC
—ns
I7
1
Data setup time 2 × t
CYC
—ns
I8
1
Start condition setup time (for repeated start
condition only)
20 × t
CYC
—ns
I9
1
Stop condition setup time 10 × t
CYC
—ns