Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 80 MHz I/O number 55

Freescale Semiconductor

Data Sheet

Document Number: MCF5213EC

Rev. 3, 05/2007

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

MCF5213

LQFP–64

10 mm x 10 mm

MAPBGA–81

10 mm x 10 mm

LQFP–100

14 mm x 14 mm

QFN–64

9mmx9mm

The MCF5213 is a member of the ColdFire

family of

reduced instruction set computing (RISC) microprocessors.

This document provides an overview of the 32-bit MCF5213

microcontroller, focusing on its highly integrated and diverse

feature set.

This 32-bit device is based on the Version 2 ColdFire core

operating at a frequency up to 80 MHz, offering high

performance and low power consumption. On-chip memories

connected tightly to the processor core include up to

256 Kbytes of flash memory and 32 Kbytes of static random

access memory (SRAM). On-chip modules include:

• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at

80 MHz running from internal flash memory with Multiply

Accumulate (MAC) Unit and hardware divider

• FlexCAN controller area network (CAN) module

• Three universal asynchronous/synchronous

receiver/transmitters (UARTs)

• Inter-integrated circuit (I2C™) bus controller

• Queued serial peripheral interface (QSPI) module

• Eight-channel 12-bit fast analog-to-digital converter

(ADC)

• Four-channel direct memory access (DMA) controller

• Four 32-bit input capture/output compare timers with

DMA support (DTIM)

• Four-channel general-purpose timer (GPT) capable of

input capture/output compare, pulse width modulation

(PWM), and pulse accumulation

• Eight-channel/Four-channel, 8-bit/16-bit pulse width

modulation timer

• Two 16-bit periodic interrupt timers (PITs)

• Programmable software watchdog timer

• Interrupt controller capable of handling 57 sources

• Clock module with 8 MHz on-chip relaxation oscillator

and integrated phase-locked loop (PLL)

• Test access/debug port (JTAG, BDM)

MCF5213 ColdFire

Microcontroller

Supports MCF5213,

MCF5212, & MCF5211

Summary of content (56 pages)

PAGE 1
Freescale Semiconductor Data Sheet Document Number: MCF5213EC Rev. 3, 05/2007 MCF5213 MCF5213 ColdFire Microcontroller Supports MCF5213, MCF5212, & MCF5211 LQFP–64 10 mm x 10 mm QFN–64 9 mm x 9 mm MAPBGA–81 10 mm x 10 mm LQFP–100 14 mm x 14 mm The MCF5213 is a member of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This document provides an overview of the 32-bit MCF5213 microcontroller, focusing on its highly integrated and diverse feature set.
PAGE 2
Table of Contents 1 2 3 4 MCF5213 Family Configurations . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
MCF5213 Family Configurations 1 MCF5213 Family Configurations Table 1. MCF5213 Family Configurations Module ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit) 5211 5212 5213 • • • System Clock 66, 80 MHz Performance (Dhrystone 2.
PAGE 4
MCF5213 Family Configurations EzPQ EzPCK EzPort EzPCS To/From PADI QSPI_DIN, QSPI_DOUT Interrupt Controller Arbiter 4 CH DMA GPTn UART 0 UART 1 UART 2 I C SWT DTIM 0 DTIM 1 DTIM 2 2 QSPI_CLK, QSPI_CSn QSPI PADI – Pin Muxing EzPD UTXDn URXDn URTSn UCTSn DTINn/DTOUTn DTIM 3 CANRX CANTX PWMn MUX JTAG_EN V2 ColdFire CPU IFP JTAG TAP AN[7:0] 32 Kbytes SRAM (4K×16)×4 ADC VRH VRL FlexCAN OEP MAC 256 Kbytes Flash (32K×16)×4 PMM PORTS (GPIO) CIM RSTI RSTO VSTBY Edge Port
PAGE 5
MCF5213 Family Configurations • • • • • • Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data paths on-chip — Up to 80 MHz processor core frequency — Sixteen general-purpose, 32-bit data and address registers — Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+) — Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 16×16 → 32 or 32×32 → 32 opera
PAGE 6
MCF5213 Family Configurations • • • • • • — Error-detection capabilities — Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs — Transmit and receive FIFO buffers I2C module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I2C bus — Master and slave modes support multiple masters — Automatic interrupt generation with programmable level Queued serial peripheral interface (QSPI) — Full-dupl
PAGE 7
MCF5213 Family Configurations • • • • • • • — Programmable center or left aligned outputs on individual channels — Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies — Emergency shutdown Two periodic interrupt timers (PITs) — 16-bit counter — Selectable as free running or count down Software watchdog timer — 32-bit counter — Low-power mode support Clock generation features — One to 48 MHz crystal, 8 MHz on-chip relaxation oscillator, or external oscillator reference option
PAGE 8
MCF5213 Family Configurations • • 1.1.
PAGE 9
MCF5213 Family Configurations 1.1.4 JTAG The MCF5213 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.
PAGE 10
MCF5213 Family Configurations 1.1.7 FlexCAN The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of FlexCAN has 16 message buffers. 1.1.8 UARTs The MCF5213 has three full-duplex UARTs that function independently.
PAGE 11
MCF5213 Family Configurations 1.1.13 General Purpose Timer (GPT) The general purpose timer (GPT) is a four-channel timer module consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, channel three, can be configured as a pulse accumulator. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
PAGE 12
MCF5213 Family Configurations 1.1.20 Reset The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset: • • • • • • • External reset input Power-on reset (POR) Watchdog timer Phase locked-loop (PLL) loss of lock PLL loss of clock Software Low-voltage detector (LVD) Control of the LVD and its associated reset and interrupt are managed by the reset controller.
PAGE 13
MCF5213 Family Configurations 100 LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS VDDPLL EXTAL XTAL VSSPLL PST3 PST2 VDD VSS PST1 PST0 PSTCLK PWM7 GPT3 GPT2 PWM5 GPT1 GPT0 VDD VSS VSTBY AN4 AN5 AN6 AN7 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 JTAG_EN UCTS2 URXD2 UTXD2 URTS2 DTIN2 DTIN3 PWM3 VDD VSS DTIN0 DTIN1 PWM1 CLKMOD1 CLKMOD0 VDD VSS AN0 AN1 AN2 AN3 VSSA VRL VRH
PAGE 14
MCF5213 Family Configurations Figure 3 shows the pinout configuration for the 81 MAPBGA.
PAGE 15
MCF5213 Family Configurations 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSS URXD1 UTXD1 UCTS1 RSTO RSTI IRQ7 IRQ4 IRQ1 ALLPST DSCLK VSS VDD DSO DSI BKPT Figure 4 shows the pinout configuration for the 64 LQFP and 64 QFN.
PAGE 16
Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 1 Control MCF5213 ColdFire Microcontroller, Rev.
PAGE 17
Freescale Semiconductor Table 3. Pin Functions by Primary and Alternate Purpose (continued) Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 Pin Group Primary Function Secondary Function Tertiary Function Quaternary Function Interrupts IRQ7 — — GPIO Low FAST IRQ6 — — GPIO Low IRQ5 — — GPIO IRQ4 — — IRQ3 — IRQ2 — MCF5213 ColdFire Microcontroller, Rev.
PAGE 18
Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 MCF5213 ColdFire Microcontroller, Rev.
PAGE 19
Freescale Semiconductor Table 3. Pin Functions by Primary and Alternate Purpose (continued) Drive Slew Rate / Pull-up / Strength / Control1 Pull-down2 Control1 Pin Group Primary Function Secondary Function Tertiary Function Quaternary Function UART 1 UCTS1 SYNCA URXD2 GPIO PDSR[15] PSRR[15] URTS1 SYNCB UTXD2 GPIO PDSR[14] URXD1 — — GPIO UTXD1 — — UCTS2 — URTS2 UART 2 MCF5213 ColdFire Microcontroller, Rev.
PAGE 20
MCF5213 Family Configurations 1.2 Reset Signals Table 4 describes signals used to reset the chip or as a reset indication. Table 4. Reset Signals 1.3 Signal Name Abbreviation Function I/O Reset In RSTI Primary reset input to the device. Asserting RSTI for at least 8 CPU clock cycles immediately resets the CPU and peripherals. I Reset Out RSTO Driven low for 1024 CPU clocks after the reset source has deasserted.
PAGE 21
MCF5213 Family Configurations 1.5 External Interrupt Signals Table 8 describes the external interrupt signals. Table 8. External Interrupt Signals 1.6 Signal Name Abbreviation External Interrupts IRQ[7:1] Function External interrupt sources. I/O I Queued Serial Peripheral Interface (QSPI) Table 9 describes the QSPI signals. Table 9.
PAGE 22
MCF5213 Family Configurations 1.8 UART Module Signals Table 11 describes the UART module signals. Table 11. UART Module Signals Signal Name Abbreviation Function I/O Transmit Serial Data Output UTXDn Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, LSB first, on this pin at the falling edge of the serial clock source.
PAGE 23
MCF5213 Family Configurations 1.11 General Purpose Timer Signals Table 14 describes the general purpose timer signals. Table 14. GPT Signals Signal Name Abbreviation General Purpose Timer Input/Output GPT[3:0] 1.12 Function I/O Inputs to or outputs from the general purpose timer module. I/O Pulse Width Modulator Signals Table 15 describes the PWM signals. Table 15. PWM Signals Signal Name Abbreviation PWM Output Channels PWM[7:0] 1.13 Function Pulse width modulated output for PWM channels.
PAGE 24
MCF5213 Family Configurations Table 16. Debug Support Signals (continued) Signal Name Abbreviation Function I/O Development Serial Input DSI Development Serial Input - Internally synchronized input that provides data input for the serial communication port to the debug module, after the DSCLK has been seen as high (logic 1). I Development Serial Output DSO Development Serial Output - Provides serial output communication for debug module responses. DSO is registered internally.
PAGE 25
Electrical Characteristics 1.15 Power and Ground Pins The pins described in Table 18 provide system power and ground to the chip. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. Table 18.
PAGE 26
Electrical Characteristics 2.1 Maximum Ratings Table 19. Absolute Maximum Ratings1, 2 Rating Symbol Value Unit VDD –0.3 to +4.0 V Clock synthesizer supply voltage VDDPLL –0.3 to +4.0 V RAM standby supply voltage VSTBY –0.3 to +4.0 V VIN –0.3 to +4.0 V EXTAL pin voltage VEXTAL 0 to 3.3 V XTAL pin voltage VXTAL 0 to 3.
PAGE 27
Electrical Characteristics 2.2 Current Consumption Table 20. Current Consumption in Low-Power Mode1,2 8MHz (Typ)3 16MHz (Typ)2 64MHz (Typ)2 80MHz (Typ)2 Units Stop mode 3 (Stop 11)4 0.13 mA 4 2.29 Mode Stop mode 2 (Stop 10) 4,5 2.80 3.08 4.76 5.38 Stop mode 0 (Stop 00)4 2.80 3.08 4.76 5.39 Wait / Doze 11.12 20.23 30.17 33.36 Run 12.40 22.74 39.92 45.47 Stop mode 1 (Stop 01) 1 All values are measured with a 3.
PAGE 28
Electrical Characteristics Table 21. Typical Active Current Consumption Specifications Symbol Typical1 Active (SRAM) Typical1 Active (Flash) Peak2 Unit IDD — 3.48 — mA 8 MHz core & I/O 7.28 13.37 19.02 16 MHz core & I/O 12.08 25.08 35.66 64 MHz core & I/O 40.14 54.62 85.01 80 MHz core & I/O 49.2 64.09 100.03 Characteristic 1 MHz core & I/O RAM standby supply current • Normal operation: VDD > VSTBY - 0.3 V • Transient condition: VSTBY - 0.3 V > VDD > VSS + 0.
PAGE 29
Electrical Characteristics Table 22.
PAGE 30
Electrical Characteristics The average chip-junction temperature (TJ) in °C can be obtained from: T J = T A + ( P D × Θ JMA ) (1) Where: TA = ambient temperature, °C ΘJA = package thermal resistance, junction-to-ambient, °C/W PD = PINT + PI/O PINT = chip internal power, IDD × VDD, watts PI/O = power dissipation on input and output pins — user determined, watts For most applications PI/O < PINT and can be ignored.
PAGE 31
Electrical Characteristics 2.5 ESD Protection Table 25.
PAGE 32
Electrical Characteristics Table 26. DC Electrical Specifications (continued)1 Characteristic Symbol Min Max Unit Output high voltage (high drive) IOH = -5 mA VOH VDD – 0.5 — V Output low voltage (high drive) IOL = 5 mA VOL — 0.5 V Output high voltage (low drive) IOH = -2 mA VOH VDD - 0.5 — V Output low voltage (low drive) IOL = 2 mA VOL — 0.5 V Weak internal pull Up device current, tested at VIL Max.
PAGE 33
Electrical Characteristics Table 27. PLL Electrical Specifications (continued) (VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic Symbol Min Max Unit Frequency un-LOCK range fUL –1.5 1.5 % fref Frequency LOCK range fLCK –0.75 0.75 % fref — — 10 .01 % fsys 7.84 8.
PAGE 34
Electrical Characteristics CLKOUT G2 G1 GPIO Outputs G3 G4 GPIO Inputs Figure 5. GPIO Timing 2.9 Reset Timing Table 29. Reset and Configuration Override Timing (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1 NUM 1 2 Characteristic Symbol Min Max Unit R1 RSTI input valid to CLKOUT High tRVCH 9 — ns R2 CLKOUT High to RSTI Input invalid tCHRI 1.
PAGE 35
Electrical Characteristics 2.10 I2C Input/Output Timing Specifications Table 30 lists specifications for the I2C input timing parameters shown in Figure 7. Table 30. I2C Input Timing Specifications between I2C_SCL and I2C_SDA Num Characteristic Min Max Units 11 Start condition hold time 2 × tCYC — ns I2 Clock low period 8 × tCYC — ns I3 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 ms I4 Data hold time 0 — ns I5 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.
PAGE 36
Electrical Characteristics Figure 7 shows timing for the values in Table 30 and Table 31. I2 I6 I5 SCL I1 I4 I3 I8 I9 I7 SDA Figure 7. I2C Input/Output Timings 2.11 Analog-to-Digital Converter (ADC) Parameters Table 32 lists specifications for the analog-to-digital converter. Table 32. ADC Parameters1 Name Characteristic Min Typical Max Unit VREFL Low reference voltage VSS — VREFH V VREFH High reference voltage VREFL — VDDA V VDDA ADC analog supply voltage 3.0 3.3 3.
PAGE 37
Electrical Characteristics Table 32. ADC Parameters1 (continued) Name Min Typical Max Unit Total harmonic distortion — −75 — dB SFDR Spurious free dynamic range — 67 to 70.3 — dB SINAD Signal-to-noise plus distortion — 61 to 63.9 — dB ENOB Effective number of bits 9.1 10.6 — Bits THD 1 2 3 4 5 6 7 Characteristic All measurements are preliminary pending full characterization, and made at VDD = 3.3V, VREFH = 3.
PAGE 38
Electrical Characteristics 2.13 DMA Timers Timing Specifications Table 33 lists timer module AC timings. Table 33. Timer Module AC Timing Specifications Characteristic1 Name 1 Min Max Unit T1 DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time 3 × tCYC — ns T2 DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width 1 × tCYC — ns All timing references to CLKOUT are given to its rising edge. 2.14 QSPI Electrical Specifications Table 34 lists QSPI timings. Table 34.
PAGE 39
Electrical Characteristics 2.15 JTAG and Boundary Scan Timing Table 35.
PAGE 40
Electrical Characteristics TCLK VIL VIH J5 Data Inputs J6 Input Data Valid J7 Data Outputs Output Data Valid J8 Data Outputs J7 Data Outputs Output Data Valid Figure 11. Boundary Scan (JTAG) Timing TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 12. Test Access Port Timing TCLK 14 TRST 13 Figure 13. TRST Timing MCF5213 ColdFire Microcontroller, Rev.
PAGE 41
Electrical Characteristics 2.16 Debug AC Timing Specifications Table 36 lists specifications for the debug AC timing parameters shown in Figure 15. Table 36. Debug AC Timing Specification 66/80 MHz Num 1 Characteristic Units Min Max D1 PST, DDATA to CLKOUT setup 4 — ns D2 CLKOUT to PST, DDATA hold 1.
PAGE 42
Electrical Characteristics Figure 15 shows BDM serial port AC timing for the values in Table 36. CLKOUT D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 15. BDM Serial Port AC Timing MCF5213 ColdFire Microcontroller, Rev.
PAGE 43
Mechanical Outline Drawings 3 Mechanical Outline Drawings This section describes the physical properties of the MCF5213 and its derivatives. 3.1 64-pin LQFP Package MCF5213 ColdFire Microcontroller, Rev.
PAGE 44
Mechanical Outline Drawings MCF5213 ColdFire Microcontroller, Rev.
PAGE 45
Mechanical Outline Drawings MCF5213 ColdFire Microcontroller, Rev.
PAGE 46
Mechanical Outline Drawings 3.2 64 QFN Package MCF5213 ColdFire Microcontroller, Rev.
PAGE 47
Mechanical Outline Drawings MCF5213 ColdFire Microcontroller, Rev.
PAGE 48
Mechanical Outline Drawings MCF5213 ColdFire Microcontroller, Rev.
PAGE 49
Mechanical Outline Drawings MCF5213 ColdFire Microcontroller, Rev.
PAGE 50
Mechanical Outline Drawings 3.3 81 MAPBGA Package MCF5213 ColdFire Microcontroller, Rev.
PAGE 51
Mechanical Outline Drawings MCF5213 ColdFire Microcontroller, Rev.
PAGE 52
Mechanical Outline Drawings 3.4 100-pin LQFP Package MCF5213 ColdFire Microcontroller, Rev.
PAGE 53
Mechanical Outline Drawings MCF5213 ColdFire Microcontroller, Rev.
PAGE 54
Revision History 4 Revision History Table 37. Revision History Revision 2 Description • • • • • • • • • • • • • • • 3 Formatting, layout, spelling, and grammar corrections. Added revision history. Corrected signal names in block diagram to match those in signal description table. Added the following footnote to the MCF5211 FlexCAN entry: “FlexCAN is available on the MCF5211 only in the 64 QFN package.” Added an entry for standby voltage (VSTBY) to the “DC electrical specifications” table.
PAGE 55
Revision History MCF5213 ColdFire Microcontroller, Rev.
PAGE 56
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.