Datasheet

MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor18
MCF5213 Family Configurations
QSPI QSPI_DIN/
EZPD
CANRX
4
URXD1 GPIO PDSR[2] PSRR[2] — 16 F3 12
QSPI_DOUT/
EZPQ
CANTX
4
UTXD1 GPIO PDSR[1] PSRR[1] — 17 G1 13
QSPI_CLK/
EZPCK
SCL URTS1
GPIO PDSR[3] PSRR[3] pull-up
8
18 G2 14
QSPI_CS3 SYNCA SYNCB GPIO PDSR[7] PSRR[7] — 12 F1 —
QSPI_CS2 — — GPIO PDSR[6] PSRR[6] — 13 F2 —
QSPI_CS1 — — GPIO PDSR[5] PSRR[5] — 19 H2 —
QSPI_CS0 SDA UCTS1 GPIO PDSR[4] PSRR[4] pull-up
8
20 H1 15
Reset
9
RSTI — — — N/A N/A pull-up
9
96 A3 59
RSTO
— — —highFAST—97B360
Test TEST — — — N/A N/A pull-down 5 C2 3
Timers, 16-bit GPT3 — PWM7 GPIO PDSR[23] PSRR[23] pull-up
10
62 D8 43
GPT2 — PWM5 GPIO PDSR[22] PSRR[22] pull-up
10
61 D9 42
GPT1 — PWM3 GPIO PDSR[21] PSRR[21] pull-up
10
59 E9 41
GPT0 — PWM1 GPIO PDSR[20] PSRR[20] pull-up
10
58 F7 40
Timers, 32-bit DTIN3 DTOUT3 PWM6 GPIO PDSR[19] PSRR[19] — 32 H3 19
DTIN2 DTOUT2 PWM4 GPIO PDSR[18] PSRR[18] — 31 J3 18
DTIN1 DTOUT1 PWM2 GPIO PDSR[17] PSRR[17] — 37 G4 23
DTIN0 DTOUT0 PWM0 GPIO PDSR[16] PSRR[16] — 36 H4 22
UART 0 UCTS0
CANRX — GPIO PDSR[11] PSRR[11] — 6 C1 4
URTS0
CANTX — GPIO PDSR[10] PSRR[10] — 9 D3 7
URXD0 — — GPIO PDSR[9] PSRR[9] — 7 D1 5
UTXD0 — — GPIO PDSR[8] PSRR[8] — 8 D2 6
Table 3. Pin Functions by Primary and Alternate Purpose (continued)
Pin
Group
Primary
Function
Secondary
Function
Tertiary
Function
Quaternary
Function
Drive
Strength /
Control
1
Slew Rate /
Control
1
Pull-up /
Pull-down
2
Pin on
100 LQFP
Pin on 81
MAPBGA
Pin on 64
LQFP/QFN