Datasheet

MCF5213 Family Configurations
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor 23
1.11 General Purpose Timer Signals
Table 14 describes the general purpose timer signals.
1.12 Pulse Width Modulator Signals
Table 15 describes the PWM signals.
1.13 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and the BDM logic.
Table 14. GPT Signals
Signal Name Abbreviation Function I/O
General Purpose Timer
Input/Output
GPT[3:0] Inputs to or outputs from the general purpose timer module. I/O
Table 15. PWM Signals
Signal Name Abbreviation Function I/O
PWM Output Channels PWM[7:0] Pulse width modulated output for PWM channels. O
Table 16. Debug Support Signals
Signal Name Abbreviation Function I/O
JTAG Enable JTAG_EN Select between debug module and JTAG signals at reset. I
Test Reset TRST This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock TCLK Used to synchronize the JTAG logic. I
Test Mode Select TMS Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
Test Data Input TDI Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output TDO Serial output for test instructions and data. TDO is tri-stateable and is
actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK Development Serial Clock - Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
Breakpoint BKPT
Breakpoint - Input used to request a manual breakpoint. Assertion of
BKPT
puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor
status/debug data signals (PST[3:0] and PSTDDATA[7:0]) as the
value 0xF. If CSR[BKD] is set (disabling normal BKPT
functionality),
asserting BKPT
generates a debug interrupt exception in the
processor.
I