Datasheet

MCF5213 Family Configurations
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor 3
1 MCF5213 Family Configurations
Table 1. MCF5213 Family Configurations
Figure 1 shows a top-level block diagram of the MCF5213. Package options for this family are described later in this document.
Module 5211 5212 5213
ColdFire Version 2 Core with MAC
(Multiply-Accumulate Unit)
•••
System Clock 66, 80 MHz
Performance (Dhrystone 2.1 MIPS) 63 up to 76
Flash / Static RAM (SRAM) 128/16 Kbytes 256/32 Kbytes
Interrupt Controller (INTC)
•••
Fast Analog-to-Digital Converter (ADC)
•••
FlexCAN 2.0B Module See note
1
1
FlexCAN is available on the MCF5211 only in the 64 QFN package.
—
•
Four-channel Direct-Memory Access (DMA)
•••
Watchdog Timer Module (WDT)
•••
Programmable Interval Timer Module (PIT) 2 2 2
Four-Channel General-Purpose Timer 3 3 3
32-bit DMA Timers 4 4 4
QSPI
•••
UARTs 3 3 3
I
2
C
•••
PWM 8 8 8
General Purpose I/O Module (GPIO)
•••
Chip Configuration and Reset Controller Module
•••
Background Debug Mode (BDM)
•••
JTAG - IEEE 1149.1 Test Access Port
2
2
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is
bonded on smaller packages.
•••
Package 64 LQFP
64 QFN
81 MAPBGA
64 LQFP
81 MAPBGA
81 MAPBGA
100 LQFP