Datasheet

Electrical Characteristics
MCF5213 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor 39
2.15 JTAG and Boundary Scan Timing
Figure 10. Test Clock Input Timing
Table 35. JTAG and Boundary Scan Timing
Num Characteristics
1
1
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
Symbol Min Max Unit
J1 TCLK frequency of operation f
JCYC
DC 1/4 f
sys/2
J2 TCLK cycle period t
JCYC
4 × t
CYC
—ns
J3 TCLK clock pulse width t
JCW
26 — ns
J4 TCLK rise and fall times t
JCRF
03ns
J5 Boundary scan input data setup time to TCLK rise t
BSDST
4—ns
J6 Boundary scan input data hold time after TCLK rise t
BSDHT
26 — ns
J7 TCLK low to boundary scan output data valid t
BSDV
033ns
J8 TCLK low to boundary scan output high Z t
BSDZ
033ns
J9 TMS, TDI input data setup time to TCLK rise t
TAPBST
4—ns
J10 TMS, TDI Input data hold time after TCLK rise t
TAPBHT
10 — ns
J11 TCLK low to TDO data valid t
TDODV
026ns
J12 TCLK low to TDO high Z t
TDODZ
08ns
J13 TRST
assert time t
TRSTAT
100 — ns
J14 TRST
setup time (negation) to TCLK high t
TRSTST
10 — ns
TCLK
V
IL
V
IH
J3 J3
J4 J4
J2
(input)