Datasheet

MCF5213 ColdFire Microcontroller, Rev. 3
MCF5213 Family Configurations
Freescale Semiconductor6
Error-detection capabilities
Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
Transmit and receive FIFO buffers
•I
2
C module
Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
Fully compatible with industry-standard I
2
C bus
Master and slave modes support multiple masters
Automatic interrupt generation with programmable level
Queued serial peripheral interface (QSPI)
Full-duplex, three-wire synchronous transfers
Up to four chip selects available
Master mode operation only
Programmable bit rates up to half the CPU clock frequency
Up to 16 pre-programmed transfers
Fast analog-to-digital converter (ADC)
Eight analog input channels
12-bit resolution
Minimum 1.125 μs conversion time
Simultaneous sampling of two channels for motor control applications
Single-scan or continuous operation
Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit
Unused analog channels can be used as digital I/O
Four 32-bit timers with DMA support
12.5 ns resolution at 80 MHz
Programmable sources for clock input, including an external clock option
Programmable prescaler
Input capture capability with programmable trigger edge on input pin
Output compare with programmable mode for the output pin
Free run and restart modes
Maskable interrupts on input capture or output compare
DMA trigger capability on input capture or output compare
Four-channel general purpose timer
16-bit architecture
Programmable prescaler
Output pulse-widths variable from microseconds to seconds
Single 16-bit input pulse accumulator
Toggle-on-overflow feature for pulse-width modulator (PWM) generation
One dual-mode pulse accumulation channel
Pulse-width modulation timer
Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution
Programmable period and duty cycle
Programmable enable/disable for each channel
Software selectable polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached
(PWM counter reaches zero) or when the channel is disabled.