Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller MAPBGA 196 (15x15) 32-Bit 166.67 MHz I/O number 55

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: MCF52277

Rev. 8, 09/2009

Freescale reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

MCF52277

MAPBGA–196

15mm x 15mm

LQFP–176

24 mm x 24 mm

Features

•Version 2 ColdFire

Core with EMAC

• Up to 159 Dhrystone 2.1 MIPS @ 166.67 MHz

• 8 Kbytes configurable cache (instruction only, data only, or

split instruction/data)

• 128 Kbytes internal SRAM

• Support for booting from SPI-compatible flash, EEPROM,

and FRAM devices

• Crossbar switch technology (XBS) for concurrent access to

peripherals or RAM from multiple bus masters

• 16 channel DMA controller

• 16- or 32-bit SDR/DDR controller

• USB 2.0 On-the-Go controller

• Liquid crystal display controller with support up to

800 × 600 pixels

• ADC and touchscreen controller

• FlexCAN module

• 4 32-bit timers with DMA support

• DMA supported serial peripheral interface (DSPI)

• 3 UARTs

•I

C bus interface

• Synchronous serial interface (SSI)

• Plus-width modulator (PWM)

• Real-time clock (RTC)

• Two programmable interrupt controllers (PIT)

MCF5227x ColdFire

Microprocessor Data Sheet

Summary of content (46 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF52277 Rev. 8, 09/2009 MCF52277 LQFP–176 24 mm x 24 mm MCF5227x ColdFire® Microprocessor Data Sheet Features • Version 2 ColdFire® Core with EMAC • Up to 159 Dhrystone 2.1 MIPS @ 166.
PAGE 2
Table of Contents 1 2 3 4 5 MCF5227x Family Comparison . . . . . . . . . . . . . . . . . . . . . . . .4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .5 3.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.2 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3.3 ADC Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
MCF52277 JTAG Oscillator Version 2 ColdFire Core 8K Configurable Cache PLL Serial Boot Facility BDM Hardware Divide 128K SRAM EMAC USB OTG LCD Controller eDMA Crossbar Switch (XBS) Peripheral Bridge FlexBus Touch Screen DSPI RTC SSI FlexCAN GPIO EPORT I2C INTC 2 PITs 3 UARTs 4 DMA Timers SDRAM Controller PWM LEGEND BDM DSPI eDMA EMAC EPORT GPIO I2 C INTC JTAG – Background debug module – DMA serial peripheral interface – Enhanced direct memory access – Enchanced multiply-accumulat
PAGE 4
MCF5227x Family Comparison 1 MCF5227x Family Comparison The following table compares the various device derivatives available within the MCF5227x family. Table 1. MCF5227x Family Configurations Module MCF52274 MCF52277 • • Core (System) Clock up to 120 MHz up to 166.67 MHz Peripheral and External Bus Clock (Core clock ÷ 2) up to 60 MHz up to 83.33 MHz Performance (Dhrystone/2.
PAGE 5
Ordering Information 2 Ordering Information Table 2. Orderable Part Numbers Freescale Part Number Description Package Speed Temperature MCF52274CLU120 MCF52274 RISC Microprocessor 176 LQFP 120 MHz –40° to +85° C MCF52277CVM160 MCF52277 RISC Microprocessor 196 MAPBGA 166.67 MHz –40° to +85° C 3 Hardware Design Considerations 3.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins.
PAGE 6
Hardware Design Considerations 3.3 ADC Power Filtering To minimize noise, an external filters is required for the ADCVDD power pin. The filter shown in Figure 4 should be connected between the board EVDD and the ADCVDD pin. The resistor and capacitors should be placed as close to the dedicated ADCVDD pin as possible. 0Ω Board EVDD ADC VDD Pin 10 µF 0.1 µF GND Figure 4. ADC VDD Power Filter 3.
PAGE 7
Hardware Design Considerations 3.5 Power Consumption Specifications All application power consumption data is lab data measured on an M52277EVB running the Freescale Linux BSP. Table 3. MCF52277 Application Power Consumption1 Core Freq. 160 MHz 1 Idle (LCD image) Idle (audio image) Button Demo Slideshow Demo MP3 Playback USB FS File Copy IVDD 61.4 59.2 84.7 96.5 89.2 89.5 EVDD 28.87 25.73 35.3 34.6 33.46 29.86 SDVDD 18.8 18.57 21.8 23.9 22.66 22.2 Total Power 221.211 207.
PAGE 8
Hardware Design Considerations Table 4. Current Consumption in Low-Power Modes1,2 (continued) System Frequency Mode 80MHz 64MHz 48MHz 32MHz 4MHz (LIMP mode) IVDD (mA) 57.0 48.8 38.9 29.7 2.7 Power (mW) 85.50 73.20 58.35 44.55 4.05 IVDD (mA) 16.1 15.1 13.4 12.5 1.3 Power (mW) 24.15 22.65 20.10 18.75 1.95 IVDD (mA) 15.9 14.9 13.2 12.4 1.3 Power (mW) 23.85 22.35 19.80 18.60 1.95 IVDD (mA) 1.8 1.8 1.8 1.8 1.3 Power (mW) 2.70 2.70 2.70 2.70 1.
PAGE 9
Pin Assignments and Reset States 4 Pin Assignments and Reset States 4.1 Signal Multiplexing The following table lists all the MCF5227x pins grouped by function. The direction column is the direction for the primary function of the pin only. Refer to Section 4, “Pin Assignments and Reset States,” for package diagrams. For a more detailed discussion of the MCF5227x signals, consult the MCF52277 Reference Manual (MCF52277RM).
PAGE 10
Pin Assignments and Reset States Pull-up (U)1 Pull-down (D) Direction2 Voltage Domain Table 6.
PAGE 11
Pin Assignments and Reset States Alternate 1 Alternate 2 SD_SDR_DQS — — — — SD_WE — — — — Voltage Domain GPIO Direction2 Signal Name Pull-up (U)1 Pull-down (D) Table 6.
PAGE 12
Pin Assignments and Reset States Alternate 1 Alternate 2 Voltage Domain GPIO Direction2 Signal Name Pull-up (U)1 Pull-down (D) Table 6.
PAGE 13
Pin Assignments and Reset States Voltage Domain MCF52274 176 LQFP MCF52277 196 MAPBGA O EVDD 76 — I EVDD 79 K10 U O EVDD 74 P8 — U I EVDD 78 M11 TDO — — O EVDD 81 L11 — TMS — U I EVDD 80 N11 — TRST — U I EVDD 77 P11 — D I EVDD 134 E10 — — — 39, 75, 114, 138, K5, F10, E5, J10 Signal Name GPIO Alternate 1 Alternate 2 Pull-up (U)1 Pull-down (D) Direction2 Table 6.
PAGE 14
Pin Assignments and Reset States If JTAG_EN is asserted, these pins default to alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins. 4.
PAGE 15
Electrical Characteristics 4.3 Pinout—196 MAPBGA The pinout for the MCF52277 package is shown below.
PAGE 16
Electrical Characteristics NOTE The parameters specified in this MCU document supersede any values found in the module specifications. 5.1 Maximum Ratings Table 7. Absolute Maximum Ratings1, 2 Characteristic Symbol Value Unit Core Supply Voltage IVDD –0.5 to +2.0 V CMOS Pad Supply Voltage EVDD –0.3 to +4.0 V SDVDD –0.3 to +4.0 V Oscillator Supply Voltage OSCVDD –0.3 to +4.0 V PLL Supply Voltage PLLVDD –0.3 to +2.0 V RTC Supply Voltage RTCVDD –0.5 to +2.
PAGE 17
Electrical Characteristics 5.2 Thermal Characteristics Table 8.
PAGE 18
Electrical Characteristics 5.3 ESD Protection Table 9. ESD Protection Characteristics1,2 Characteristic ESD Target for Human Body Model Symbol Value Unit HBM 2000 V 1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements.
PAGE 19
Electrical Characteristics Table 10. DC Electrical Specifications (continued) Characteristic Symbol Min Max 1.4 2.1 2.4 — — — — — — 0.3 0.3 0.5 Iin –1.0 1.0 μA Weak Internal Pull-Up Device Current, tested at VIL Max.1 IAPU –10 –130 μA Input Capacitance 2 All input-only pins All input/output (three-state) pins Cin — — 7 7 Symbol Min Max Unit fref_crystal fref_ext 16 16 251 66.671 MHz MHz fsys 166.67 83.
PAGE 20
Electrical Characteristics Table 11. PLL Electrical Characteristics (continued) Num Characteristic Symbol Min Max Unit 13 Discrete load capacitance for XTAL Discrete load capacitance for EXTAL CL_XTAL CL_EXTAL — 2 × (CL – CS_XTAL – CS_EXTAL – CS_PCB)7 pF 14 Frequency un-LOCK Range fUL –4.0 4.0 % fsys 15 Frequency LOCK Range fLCK –2.0 2.
PAGE 21
Electrical Characteristics Table 12. ASP Electrical Characteristics (continued) Characteristic Symbol Min Typical Max Unit Conversion Time tADC 15 — 32 tAIC cycles Sample Time tADS 3 — 20 tAIC cycles Multiplexer Settling Time tAMS — — 3 tAIC cycles Zero-scale Error ZE — ±4 ±12 lsb1 Full-scale Error FE — ±320 ±370 lsb1 CAIN — — 34 pF Input Capacitance 1 A least significant bit (lsb) is a unit of voltage equal to the smallest resolution of the ADC.
PAGE 22
Electrical Characteristics Table 13. FlexBus AC Timing Specifications (continued) Num Characteristic Symbol Min Max Unit FB4 Data Input Setup tDVFBCH 3.5 — ns FB5 Data Input Hold tDIFBCH 0 — ns FB6 Transfer Acknowledge (TA) Input Setup tCVFBCH 4 — ns FB7 Transfer Acknowledge (TA) Input Hold tCIFBCH 0 — ns Notes 1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2.2, “DDR SDRAM AC Timing Specifications,” for SD_CS[3:0] timing.
PAGE 23
Electrical Characteristics S0 S1 S2 S3 FB_CLK FB1 FB3 ADDR[23:0] FB_A[23:0] FB2 FB_D[31:X] ADDR[31:X] DATA FB_R/W FB_TS FB_CSn, FB_BE/BWEn FB_OE FB6 FB7 FB_TA Figure 10. Flexbus Write Timing 5.7.2 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. 5.7.2.
PAGE 24
Electrical Characteristics Table 14. SDR Timing Specifications (continued) Num Characteristic Symbol Min Max Unit SD8 SD_DQS[3:2] input hold relative to SD_CLK tDQISDCH SD9 Data (D[31:0]) Input Setup relative to SD_CLK (reference only) tDVSDCH 0.25 × SD_CLK — ns SD10 Data Input Hold relative to SD_CLK (reference only) tDISDCH 1.0 — ns SD11 Data (D[31:0]) and Data Mask(SD_DQM[3:0]) Output Valid tSDCHDMV — 0.
PAGE 25
Electrical Characteristics SD2 SD1 SD_CLK SD5 SD_CSn, SD_RAS, SD_CAS, SD_WE SD3 CMD 3/4 MCLK Reference SD4 A[23:0], SD_BA[1:0] ROW COL tDQS SDDM SD6 SD_SDR_DQS (Measured at Output Pin) Board Delay SD_DQS[3:2] SD8 (Measured at Input Pin) SD7 Board Delay Delayed SD_CLK SD9 D[31:0] from Memories WD1 NOTE: Data driven from memories relative to delayed memory clock. WD2 WD3 WD4 SD10 Figure 12. SDR Read Timing 5.7.2.
PAGE 26
Electrical Characteristics Table 15. DDR Timing Specifications (continued) Num Characteristic Symbol Min Max Unit Notes DD8 Data and Data Mask Output Hold (DQS→DQ) Relative to DQS (DDR Write Mode) tDQDMI 1.0 — ns 7 DD9 Input Data Skew Relative to DQS (Input Setup) tDVDQ — 1 ns 8 tDIDQ 0.25 × SD_CLK + 0.5ns — ns 9 0.
PAGE 27
Electrical Characteristics DD1 DD2 SD_CLK DD3 SD_CLK DD5 SD_CSn, SD_WE, SD_RAS, SD_CAS CMD DD4 A[13:0] ROW COL DD11 SD_DQS[3:2] DD6 DD7 SD_DM[3:2] D[31:16] WD1 WD2 WD3 WD4 DD8 Figure 13. DDR Write Timing MCF5227x ColdFire® Microprocessor Data Sheet, Rev.
PAGE 28
Electrical Characteristics DD1 DD2 SD_CLK DD3 SD_CLK CL=2 DD5 SD_CSn,SD_WE, SD_RAS, SD_CAS CMD CL=2.5 DD4 A[13:0] ROW COL DD9 DQS Read Postamble DQS Read Preamble CL = 2 SD_DQS3/SD_DQS2 DD10 D[31:24]/D[23:16] WD1 DQS Read Preamble CL = 2.5 SD_DQS3/SD_DQS2 WD2 WD3 WD4 DQS Read Postamble D[31:24]/D[23:16] WD1 WD2 WD3 WD4 Figure 14. DDR Read Timing Table 16. DDR Clock Crossover Specifications Symbol 1 Characteristic Min Max Unit VMP Clock output mid-point voltage 1.05 1.
PAGE 29
Electrical Characteristics 5.8 General Purpose I/O Timing Table 17. GPIO Timing1 Num 1 Characteristic Symbol Min Max Unit G1 FB_CLK High to GPIO Output Valid tCHPOV — 10 ns G2 FB_CLK High to GPIO Output Invalid tCHPOI 1.5 — ns G3 GPIO Input Valid to FB_CLK High tPVCH 9 — ns G4 FB_CLK High to GPIO Input Invalid tCHPI 1.
PAGE 30
Electrical Characteristics FB_CLK R1 R2 R3 RESET R4 R4 RSTOUT R8 R5 R6 R7 Configuration Overrides*: (RCON, Override pins) Figure 17. RESET and Configuration Override Timing NOTE Refer to the CCM chapter of the MCF52277 Reference Manual for more information. 5.10 LCD Controller Timing Specifications This sections lists the timing specifications for the LCD Controller. Table 19.
PAGE 31
Electrical Characteristics Non-display Region LCD_VSYNC Display Region T3 T1 T4 T2 LCD_HSYNC LCD_OE LCD_D[17:0] Line Y Line 1 T5 T6 Line Y XMAX T7 LCD_HSYNC LCD_LSCLK LCD_OE LCD_D[15:0] (1,1) (1,2) (1,X) Figure 19. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 20.
PAGE 32
Electrical Characteristics XMAX LCD_LSCLK LCD_D D1 D320 D2 D320 T1 LCD_SPL_SPR T2 T3 T2 LCD_HSYNC T4 T4 LCD_CLS T5 LCD_PS T6 T7 T7 LCD_REV Figure 20. Sharp TFT Panel Timing Table 21.
PAGE 33
Electrical Characteristics T1 T1 LCD_VSYNC T3 T2 T4 XMAX T2 LCD_HSYNC LCD_LSCLK Ts LCD_D[15:0] Figure 21. Non-TFT Mode Panel Timing Table 22. Non-TFT Mode Panel Timing Num Characteristic Min Value Unit T1 LCD_HSYNC to LCD_VSYNC delay 2 HWAIT2 + 2 Tpix T2 LCD_HSYNC pulse width 1 HWIDTH + 1 Tpix T3 LCD_VSYNC to LCD_LSCLK — 0 ≤ T3 ≤ Ts — T4 LCD_LSCLK to LCD_HSYNC 1 HWAIT1 + 1 Tpix Note: Ts is the LCD_LSCLK period while Tpix is the pixel clock period.
PAGE 34
Electrical Characteristics Table 23. USB On-Chip Transceiver DC Characteristics (continued) Characteristic Condition Symbol Min Typ Max Unit P side Impedance Driven ZP 6.25 8.25 11.25 Ω M side Impedance Driven ZM 6.25 8.25 11.25 Ω ZMatching — 0.17 0.
PAGE 35
Electrical Characteristics Table 26. SSI Timing—Master Modes1 (continued) Num Characteristic Symbol Min Max Unit S5 SSI_BCLK to SSI_FS output valid — 10 ns S6 SSI_BCLK to SSI_FS output invalid 0 — ns S7 SSI_BCLK to SSI_TXD valid — 10 ns S8 SSI_BCLK to SSI_TXD invalid / high impedence 0 — ns S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 10 — ns S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns Notes 1 All timings specified with a capactive load of 25pF.
PAGE 36
Electrical Characteristics S1 S2 S2 SSI_MCLK (Output) S3 SSI_BCLK (Output) S4 S4 S5 S6 SSI_FS (Output) S9 S10 SSI_FS (Input) S7 S7 S8 S8 SSI_TXD S9 S10 SSI_RXD Figure 22. SSI Timing—Master Modes S11 SSI_BCLK (Input) S12 S12 S15 S16 SSI_FS (Output) S13 S14 SSI_FS (Input) S15 S16 S16 S15 SSI_TXD S17 S18 SSI_RXD Figure 23. SSI Timing—Slave Modes 5.13 I2C Timing Specifications Table 28 lists specifications for the I2C input timing parameters shown in Figure 24. Table 28.
PAGE 37
Electrical Characteristics Table 28. I2C Input Timing Specifications between SCL and SDA (continued) Num Characteristic Min Max Unit I5 I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 1 ms I6 Clock high time 4 — tcyc I7 Data setup time 0 — ns I8 Start condition setup time (for repeated start condition only) 2 — tcyc I9 Stop condition setup time 2 — tcyc Min Max Unit Table 29 lists specifications for the I2C output timing parameters shown in Figure 24. Table 29.
PAGE 38
Electrical Characteristics 5.14 DMA Timer Timing Specifications Table 30 lists timer module AC timings. Table 30. Timer Module AC Timing Specifications Num 5.15 Characteristic Min Max Unit T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — tCYC T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — tCYC DSPI Timing Specifications The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many of the transfer attributes are programmable.
PAGE 39
Electrical Characteristics DS3 DS4 DSPI_PCSn DS1 DS2 DSPI_SCK (DCTARn[CPOL] = 0) DS2 DSPI_SCK (DCTARn[CPOL] = 1) DS7 DS8 DSPI_SIN First Data Data DS6 DSPI_SOUT Last Data DS5 First Data Data Last Data Figure 25. DSPI Classic SPI Timing—Master Mode DSPI_SS DS1 DSPI_SCK (DCTARn[CPOL] = 0) DS2 DS2 DSPI_SCK (DCTARn[CPOL] = 1) DS13 DSPI_SOUT DS10 First Data DS11 DSPI_SIN DS9 Data Last Data Data Last Data DS14 DS12 First Data Figure 26. DSPI Classic SPI Timing—Slave Mode 5.
PAGE 40
Electrical Characteristics Table 32. SBF AC Timing Specifications Num 1 Characteristic Symbol Min Max Unit Notes tSBFCK 30 — ns 1 SB1 SBF_CK Cycle Time SB2 SBF_CK High/Low Time — 30% — tSBFCK SB3 SBF_CS to SBF_CK delay — tSBFCK – 2.0 — ns SB4 SBF_CK to SBF_CS delay — tSBFCK – 2.
PAGE 41
Electrical Characteristics Table 33.
PAGE 42
Electrical Characteristics TCLK VIL VIH J9 TDI TMS J10 Input Data Valid J11 TDO Output Data Valid J12 TDO J11 TDO Output Data Valid Figure 30. Test Access Port Timing TCLK J14 TRST J13 Figure 31. TRST Timing 5.18 Debug AC Timing Specifications Table 34 lists specifications for the debug AC timing parameters shown in Figure 32. Table 34. Debug AC Timing Specification Num 1 Characteristic Min Max Units D0 PSTCLK cycle time 1 1 1/fSYS D1 PSTCLK rising to PSTDDATA valid — 3.
PAGE 43
Package Information D0 PSTCLK D2 D1 PSTDDATA[7:0] Figure 32. Real-Time Trace AC Timing D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 33. BDM Serial Port AC Timing 6 Package Information The latest package outline drawings are available on the product summary pages on our web site: http://www.freescale.com/coldfire. The following table lists the case outline numbers per device. Use these numbers in the web page’s keyword search engine to find the latest package outline drawings.
PAGE 44
Revision History 8 Revision History Table 36 summarizes revisions to this document. f Table 36. MCF52277 Data Sheet Revision History Rev. No. Date of Release Summary of Changes 3 02/2008 Initial public revision. 4 05/2008 Corrected MCF52274 order number from MCF52274CAB120 to MCF52274CLU120 in Table 2 5 07/2008 Corrected MCF52277CVM166 part number to MCF52277CVM160 in Table 2. Although, this device has a maximum rated frequency of 166.67 MHz. 6 07/2008 Added data to Section 3.
PAGE 45
Revision History MCF5227x ColdFire® Microprocessor Data Sheet, Rev.
PAGE 46
How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.