Datasheet

MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor22
NOTE
The processor drives the data lines during the first clock cycle of the transfer with the full
32-bit address. This may be ignored by standard connected devices using non-multiplexed
address and data buses. However, some applications may find this feature beneficial.
The address and data busses are muxed between the FlexBus and SDRAM controller. At
the end of the read and write bus cycles the address signals are indeterminate.
Figure 9. FlexBus Read Timing
FB4 Data Input Setup t
DVFBCH
3.5 — ns
FB5 Data Input Hold t
DIFBCH
0—ns
FB6 Transfer Acknowledge (TA
) Input Setup t
CVFBCH
4—ns
FB7 Transfer Acknowledge (TA
) Input Hold t
CIFBCH
0—ns
1
Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.7.2.2, “DDR SDRAM AC Timing
Specifications,” for SD_CS[3:0] timing.
2
The FlexBus supports programming an extension of the address hold. Please consult the device reference manual for more
information.
Table 13. FlexBus AC Timing Specifications (continued)
Num Characteristic Symbol Min Max Unit Notes
FB_CLK
FB_R/W
S0 S1 S2 S3
FB_TS
FB_A[23:0]
FB_D[31:X]
FB_CSn, FB_OE,
FB_BE/BWE
n
FB_TA
DATA
ADDR[31:X]
ADDR[23:0]
FB3
FB1
FB2 FB5
FB4
FB7
FB6