Datasheet

Electrical Characteristics
MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 23
Figure 10. Flexbus Write Timing
5.7.2 SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard
SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time.
5.7.2.1 SDR SDRAM AC Timing Specifications
The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus
clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller
is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the
device for each data beat of an SDR read. The processor accomplishes this by asserting a signal named SD_SDR_DQS during
read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the
SD_SDR_DQS signal and its usage.
Table 14. SDR Timing Specifications
Num Characteristic Symbol Min Max Unit Notes
Frequency of Operation 60 83.33 MHz
1
SD1 Clock Period t
SDCK
12.0 16.67 ns
2
SD2 Pulse Width High t
SDCKH
0.45 0.55 SD_CLK
3
SD3 Pulse Width Low t
SDCKH
0.45 0.55 SD_CLK
3
SD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Valid
t
SDCHACV
—0.5× SD_CLK
+1.0
ns
SD5 Address, SD_CKE, SD_CAS
, SD_RAS, SD_WE, SD_BA,
SD_CS[1:0] - Output Hold
t
SDCHACI
2.0 — ns
SD6 SD_SDR_DQS Output Valid t
DQSOV
—Self timedns
4
SD7 SD_DQS[3:2] input setup relative to SD_CLK t
DQVSDCH
0.25 ×
SD_CLK
0.40 × SD_CLK ns
5
FB_CLK
FB_R/W
FB_TS
FB_OE
S0 S2 S3
DATA
S1
ADDR[31:X]
FB_A[23:0]
FB_D[31:X]
ADDR[23:0]
FB_CSn, FB_BE/BWEn
FB_TA
FB3
FB1
FB2
FB7
FB6