Datasheet

Electrical Characteristics
MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 25
Figure 12. SDR Read Timing
5.7.2.2 DDR SDRAM AC Timing Specifications
When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive
data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 15. DDR Timing Specifications
Num Characteristic Symbol Min Max Unit Notes
Frequency of Operation t
DDCK
60 83.33 MHz
1
DD1 Clock Period t
DDSK
12.0 16.67 ns
2
DD2 Pulse Width High t
DDCKH
0.45 0.55 SD_CLK
3
DD3 Pulse Width Low t
DDCKL
0.45 0.55 SD_CLK
3
DD4 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS
[1:0] - Output Valid
t
SDCHACV
—0.5× SD_CLK
+1.0
ns
4
DD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,
SD_CS[1:0] - Output Hold
t
SDCHACI
2.0 — ns
DD6 Write Command to first DQS Latching Transition t
CMDVDQ
— 1.25 SD_CLK
DD7 Data and Data Mask Output Setup (DQ→DQS)
Relative to DQS (DDR Write Mode)
t
DQDMV
1.5 — ns
5
6
SD_CLK
SD_CSn,
SDDM
D[31:0]
A[23:0],
SD_RAS
,
SD_BA[1:0]
CMD
ROW
SD1
SD4
COL
WD1 WD2 WD3 WD4
SD9
3/4 MCLK
SD_SDR_DQS
SD_DQS[3:2]
Delayed
SD10
SD7
Board Delay
SD8
Board Delay
SD6
tDQS
Reference
SD_CLK
from
Memories
(Measured at Output Pin)
(Measured at Input Pin)
SD5
NOTE: Data driven from memories relative
to delayed memory clock.
SD_WE
SD_CAS,
SD2
SD3