Datasheet

MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor28
Figure 14. DDR Read Timing
Figure 15. SD_CLK and SD_CLK
Crossover Timing
Table 16. DDR Clock Crossover Specifications
Symbol Characteristic Min Max Unit
V
MP
Clock output mid-point voltage 1.05 1.45 V
V
OUT
Clock output voltage level –0.3 SD_VDD + 0.3 V
V
ID
Clock output differential voltage (peak to peak swing) 0.7 SD_VDD + 0.6 V
V
IX
Clock crossing point voltage
1
1
The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0] and
SDCLK
[1:0] signals.
1.05 1.45 V
SD_CLK
SD_CS
n,SD_WE,
SD_DQS3/SD_DQS2
D[31:24]/D[23:16]
A[13:0]
SD_RAS
, SD_CAS
CMD
ROW
DD1
DD5
DD4
WD1WD2WD3WD4
SD_DQS3/SD_DQS2
DD9
SD_CLK
DD3
DD2
D[31:24]/D[23:16]
WD1 WD2 WD3 WD4
DD10
CL=2
CL=2.5
COL
DQS Read
Preamble
DQS Read
Postamble
DQS Read
Preamble
DQS Read
Postamble
CL = 2.5 CL = 2
SD_CLK
SD_CLK
V
IX
V
MP
V
IX
V
ID