Datasheet

Electrical Characteristics
MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 35
S5 SSI_BCLK to SSI_FS output valid — 10 ns
S6 SSI_BCLK to SSI_FS output invalid 0 — ns
S7 SSI_BCLK to SSI_TXD valid — 10 ns
S8 SSI_BCLK to SSI_TXD invalid / high impedence 0 — ns
S9 SSI_RXD / SSI_FS input setup before SSI_BCLK 10 — ns
S10 SSI_RXD / SSI_FS input hold after SSI_BCLK 0 — ns
1
All timings specified with a capactive load of 25pF.
2
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
3
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does not
exceed 4 x f
SYS
.
Table 27. SSI Timing—Slave Modes
1
1
All timings specified with a capactive load of 25 pF.
Num Characteristic Symbol Min Max Unit Notes
S11 SSI_BCLK cycle time t
BCLK
4 × 1/f
SYS
—ns
S12 SSI_BCLK pulse width high / low 45% 55% t
BCLK
S13 SSI_FS input setup before SSI_BCLK 10 — ns
S14 SSI_FS input hold after SSI_BCLK 2 — ns
S15 SSI_BCLK to SSI_TXD / SSI_FS output valid — 10 ns
S16 SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
0— ns
S17 SSI_RXD setup before SSI_BCLK 10 — ns
S18 SSI_RXD hold after SSI_BCLK 2 — ns
Table 26. SSI Timing—Master Modes
1
(continued)
Num Characteristic Symbol Min Max Unit Notes