Datasheet

MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor36
Figure 22. SSI Timing—Master Modes
Figure 23. SSI Timing—Slave Modes
5.13 I
2
C Timing Specifications
Table 28 lists specifications for the I
2
C input timing parameters shown in Figure 24.
Table 28. I
2
C Input Timing Specifications between SCL and SDA
Num Characteristic Min Max Unit
I1 Start condition hold time 2 — t
cyc
I2 Clock low period 8 — t
cyc
I3 I2C_SCL/I2C_SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) — 1 ms
I4 Data hold time 0 — ns
SSI_MCLK
(Output)
SSI_BCLK
(Output)
SSI_FS
(Output)
SSI_TXD
SSI_RXD
S1 S2 S2
S3
S4 S4
S5
S6
S7
S8
S8
S9 S10
S7
SSI_FS
(Input)
S9
S10
SSI_BCLK
(Input)
SSI_FS
(Input)
SSI_TXD
SSI_RXD
S11
S12
S12
S14
S15
S16
S16
S17 S18
S15
S13
SSI_FS
(Output)
S15
S16