Datasheet

Electrical Characteristics
MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor 37
Table 29 lists specifications for the I
2
C output timing parameters shown in Figure 24.
Figure 24 shows timing for the values in Table 29 and Table 28.
Figure 24. I
2
C Input/Output Timings
I5 I2C_SCL/I2C_SDA fall time (V
IH
= 2.4 V to V
IL
=0.5 V) — 1 ms
I6 Clock high time 4 — t
cyc
I7 Data setup time 0 — ns
I8 Start condition setup time (for repeated start condition only) 2 — t
cyc
I9 Stop condition setup time 2 — t
cyc
Table 29. I
2
C Output Timing Specifications between SCL and SDA
Num Characteristic Min Max Unit
I1
1
1
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Tab le 2 9. The I
2
C interface is designed
to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is
affected by the prescale and division values programmed into the IFDR; however, the numbers given in Ta bl e 2 9
are minimum values.
Start condition hold time 6 — t
cyc
I2
1
Clock low period 10 — t
cyc
I3
2
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
I2C_SCL/I2C_SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V) — — µs
I4
1
Data hold time 7 — t
cyc
I5
3
3
Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V) — 3 ns
I6
1
Clock high time 10 — t
cyc
I7
1
Data setup time 2 — t
cyc
I8
1
Start condition setup time (for repeated start condition only) 20 — t
cyc
I9
1
Stop condition setup time 10 — t
cyc
Table 28. I
2
C Input Timing Specifications between SCL and SDA (continued)
Num Characteristic Min Max Unit
I2
I6
I1
I4
I8
I9
I5
I3
I2C_SCL
I2C_SDA
I7