Datasheet

MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor38
5.14 DMA Timer Timing Specifications
Table 30 lists timer module AC timings.
5.15 DSPI Timing Specifications
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with both master and slave operations. Many
of the transfer attributes are programmable. Table 31 provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the MCF52277 Reference Manual for information on the modified transfer formats used for
communicating with slower peripheral devices.
Table 30. Timer Module AC Timing Specifications
Num Characteristic Min Max Unit
T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time 3 — t
CYC
T2 DT0IN / DT1IN / DT2IN / DT3IN pulse width 1 — t
CYC
Table 31. DSPI Module AC Timing Specifications
1
1
Timings shown are for DMCR[MTFE] = 0 (classic SPI) and DCTARn[CPHA] = 0. Data is sampled on the DSPI_SIN pin on the
odd-numbered DSPI_SCK edges and driven on the DSPI_SOUT pin on even-numbered DSPI edges.
Num Characteristic Symbol Min Max Unit Notes
DS1 DSPI_SCK Cycle Time t
SCK
4 x 1/f
SYS
—ns
2
2
When in master mode, the baud rate is programmable in DCTARn[PBR] and DCTARn[BR].
DS2 DSPI_SCK Duty Cycle — (tsck ÷ 2) – 2.0 (tsck ÷ 2) + 2.0 ns
Master Mode
DS3 DSPI_PCSn to DSPI_SCK delay t
CSC
(2 × 1/f
SYS
) – 2.0 — ns
3
3
The DSPI_PCSn to DSPI_SCK delay is programmable in DCTARn[PCSSCK] and DCTARn[CSSCK].
DS4 DSPI_SCK to DSPI_PCSn delay t
ASC
(2 × 1/f
SYS
) – 3.0 — ns
4
4
The DSPI_SCK to DSPI_PCSn delay is programmable in DCTARn[PASC] and DCTARn[ASC].
DS5 DSPI_SCK to DSPI_SOUT valid — — 5 ns
DS6 DSPI_SCK to DSPI_SOUT invalid — –5 — ns
DS7 DSPI_SIN to DSPI_SCK input setup — 9 — ns
DS8 DSPI_SCK to DSPI_SIN input hold — 0 — ns
Slave Mode
DS9 DSPI_SCK to DSPI_SOUT valid — — 4 ns
DS10 DSPI_SCK to DSPI_SOUT invalid — 0 — ns
DS11 DSPI_SIN to DSPI_SCK input setup — 2 — ns
DS12 DSPI_SCK to DSPI_SIN input hold — 7 — ns
DS13 DSPI_SS
active to DSPI_SOUT driven — — 20 ns
DS14 DSPI_SS
inactive to DSPI_SOUT not driven — — 18 ns