Datasheet

MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor40
Figure 27. SBF Timing
5.17 JTAG and Boundary Scan Timing Specifications
Table 32. SBF AC Timing Specifications
Num Characteristic Symbol Min Max Unit Notes
SB1 SBF_CK Cycle Time t
SBFCK
30 — ns
1
1
At reset, the SBF_CK cycle time is t
REF
× 67. The first byte of data read from the serial memory contains a divider
value that is used to set the SBF_CK cycle time for the duration of the serial boot process.
SB2 SBF_CK High/Low Time — 30% — t
SBFCK
SB3 SBF_CS to SBF_CK delay — t
SBFCK
– 2.0 — ns
SB4 SBF_CK to SBF_CS
delay — t
SBFCK
– 2.0 — ns
SB5 SBF_CK to SBF_DO valid — — 12 ns
SB6 SBF_CK to SBF_DO invalid — 0 — ns
SB7 SBF_DI to SBF_SCK input setup — 6 — ns
SB8 SBF_CK to SBF_DI input hold — 0 — ns
Table 33. JTAG and Boundary Scan Timing
Num Characteristic
1
Symbol Min Max Unit
J1 TCLK Frequency of Operation f
JCYC
DC 1/4 f
sys/2
J2 TCLK Cycle Period t
JCYC
4—t
CYC
J3 TCLK Clock Pulse Width t
JCW
26 — ns
J4 TCLK Rise and Fall Times t
JCRF
03ns
J5 Boundary Scan Input Data Setup Time to TCLK Rise t
BSDST
4—ns
J6 Boundary Scan Input Data Hold Time after TCLK Rise t
BSDHT
26 — ns
J7 TCLK Low to Boundary Scan Output Data Valid t
BSDV
033ns
J8 TCLK Low to Boundary Scan Output High Z t
BSDZ
033ns
SBF_CS
SBF_DO
SBF_DI
Data
Last Data
First Data
First Data Data Last Data
SBF_CK
SB3
SB1
SB2
SB2
SB8SB7
SB6 SB5
SB4