Datasheet

MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor42
Figure 30. Test Access Port Timing
Figure 31. TRST
Timing
5.18 Debug AC Timing Specifications
Table 34 lists specifications for the debug AC timing parameters shown in Figure 32.
Table 34. Debug AC Timing Specification
Num Characteristic Min Max Units
D0 PSTCLK cycle time 1 1 1/f
SYS
D1 PSTCLK rising to PSTDDATA valid — 3.0 ns
D2 PSTCLK rising to PSTDDATA invalid 1.5 — ns
D3 DSI-to-DSCLK setup 1 — PSTCLK
D4
1
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative
to the rising edge of PSTCLK.
DSCLK-to-DSO hold 4 — PSTCLK
D5 DSCLK cycle time 5 — PSTCLK
D6 BKPT assertion time 1 — PSTCLK
Input Data Valid
Output Data Valid
Output Data Valid
TCLK
TDI
TDO
TDO
TDO
TMS
V
IL
V
IH
J9 J10
J11
J12
J11
TCLK
TRST
J13
J14