Datasheet

MCF5227x ColdFire
®
Microprocessor Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor6
3.3 ADC Power Filtering
To minimize noise, an external filters is required for the ADCV
DD
power pin. The filter shown in Figure 4 should be connected
between the board EV
DD
and the ADCV
DD
pin. The resistor and capacitors should be placed as close to the dedicated ADCV
DD
pin as possible.
Figure 4. ADC V
DD
Power Filter
3.4 Supply Voltage Sequencing
The relationship between SDV
DD
and EV
DD
is non-critical during power-up and power-down sequences. Both SDV
DD
(2.5V
or 3.3V) and EV
DD
are specified relative to IV
DD
.
3.4.1 Power Up Sequence
If EV
DD
/SDV
DD
are powered up with IV
DD
at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers
connected to the EV
DD
/SDV
DD
to be in a high impedance state. There is no limit on how long after EV
DD
/SDV
DD
powers up
before IV
DD
must powered up. IV
DD
should not lead the EV
DD
, SDV
DD
or PLLV
DD
by more than 0.4 V during power ramp-up,
or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than
500 us to avoid turning on the internal ESD protection clamp diodes.
3.4.2 Power Down Sequence
If IV
DD
/PLLV
DD
are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high
impedance state. There is no limit on how long after IV
DD
and PLLV
DD
power down before EV
DD
or SDV
DD
must power
down. IV
DD
should not lag EV
DD
, SDV
DD
, or PLLV
DD
going low by more than 0.4 V during power down or there will be
undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
1. Drop IV
DD
/PLLV
DD
to 0 V.
2. Drop EV
DD
/SDV
DD
supplies.
Board EV
DD
0 Ω
0.1 µF
ADC V
DD
Pin
10 µF
GND