Datasheet

4-16 MCF5307 User’s Manual
Cache Operation
4.9.3.2 Write Miss
The cache controller handles processor writes that miss in the cache differently for
write-through and copyback regions. Write misses to copyback regions cause the cache line
to be read from system memory, as shown in Figure 4-6.
Figure 4-6. Write-Miss in Copyback Mode
The new cache line is then updated with write data and the M bit is set for the line, leaving
it in modified state. Write misses to write-through regions write directly to memory without
loading the corresponding cache line into the cache.
4.9.3.3 Read Hit
On a read hit, the cache provides the data to the processor core and the cache line state
remains unchanged. If the cache mode changes for a specific region of address space, lines
in the cache corresponding to that region that contain modified data are not pushed out to
memory when a read hit occurs within that line. First execute a CPUSHL instruction or set
CACR[CINVA] before switching the cache mode.
4.9.3.4 Write Hit
The cache controller handles processor writes that hit in the cache differently for
write-through and copyback regions. For write hits to a write-through region, portions of
cache lines corresponding to the size of the access are updated with the data. The data is
Cache Line
System
V = 1
M = 0
1
. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line.
Memory
V = 0
M = 0
0x0C 0x000x08 0x04
2. The cache line (characters A–P) is updated from system memory, and line is marked valid.
X
ABCD EFGH IJKL MNOP
3. After the cache line is filled, the write that initiated the write miss (the character X) completes to 0x0B.
V = 1
M = 1
0x0C 0x000x08 0x04
0x0C 0x000x08 0x04
ABCD EXGH IJKL MNOP
MCF5307
MCF5307
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...