Datasheet

Chapter 4. Local Memory 4-23
Cache Registers
NOTE:
The SIM MBAR region should be mapped as cache-inhibited
through an ACR.
Table 4-5 describes ACRn fields.
I
31 2423 1615141312 76543 2 10
Field Address Base Address Mask E S — CM — W —
Reset Uninitialized 0 Uninitialized
R/W Write (R/W by debug module)
Rc ACR0: 0x004; ACR1: 0x005
Figure 4-9. Access Control Register Format (ACRn)
Table 4-5. ACRn Field Descriptions
Bits Name Description
31–24 Address
base
Address base. Compared with address bits A[31:24]. Eligible addresses that match are
assigned the access control attributes of this register.
23–16 Address
mask
Address mask. Setting a mask bit causes the corresponding address base bit to be ignored.
The low-order mask bits can be set to define contiguous regions larger than 16 Mbytes. The
mask can define multiple noncontiguous regions of memory.
15 E Enable. Enables or disables the other ACRn bits.
0 Access control attributes disabled
1 Access control attributes enabled
14–13 S Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this
address range or if the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
12–7 — Reserved; should be cleared.
6–5 CM Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are
described in Section 4.9.2, “Cache-Inhibited Accesses.”
00 Cacheable, write-through
01 Cacheable, copyback
10 Cache-inhibited, precise
11 Cache-inhibited, imprecise
4–3 — Reserved, should be cleared.
2 W Write protect. Selects the write privilege of the memory region.
0 Read and write accesses permitted
1 Write accesses not permitted
1–0 — Reserved, should be cleared.
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