Datasheet

Chapter 4. Local Memory 4-25
Cache Operation Summary
move.l d0,a0 ;set = 0, way = d0
cmpi.l #4,d0 ;flushed all the ways?
bne setloop
rts
The following CACR loads assume the default cache mode is copyback.
CacheLoadAndLock:
move.l #0xA1000100,d0; enable and invalidate cache ...
movec d0,cacr ; ... in the CACR
The following code preloads half of the cache (4 Kbytes). It assumes a contiguous block of
data is to be mapped into the cache, starting at a 0-modulo-4K address.
move.l #256,d0 ;256 16-byte lines in 4K space
lea data_,a0 ; load pointer defining data area
CacheLoop:
tst.b (a0) ;touch location + load into data cache
lea 16(a0),a0 ;increment address to next line
subq.l #1,d0 ;decrement loop counter
bne.b CacheLoop ;if done, then exit, else continue
; A 4K region has been loaded into levels 0 and 1 of the 8K cache. lock it!
move.l #0xA8000100,d0 ;set the cache lock bit ...
movec d0,cacr ; ... in the CACR
rts
align 16
4.12 Cache Operation Summary
This section gives operational details for the cache and presents cache-line state diagrams.
4.12.1 Cache State Transitions
Using the V and M bits, the cache supports a line-based protocol allowing individual cache
lines to be invalid, valid, or modified. To maintain memory coherency, the cache supports
both write-through and copyback modes, specified by the corresponding ACR[CM], or
CACR[DCM] if no ACR matches.
Read or write misses to copyback regions cause the cache controller to read a cache line
from memory into the cache. If available, tag and data from memory update an invalid line
in the selected set. The line state then changes from invalid to valid by setting the V bit. If
all lines in the row are already valid or modified, the pseudo-round-robin replacement
algorithm selects one of the four lines and replaces the tag and data. Before replacement,
modified lines are temporarily buffered and later copied back to memory after the new line
has been read from memory.
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