Datasheet

4-26 MCF5307 User’s Manual
Cache Operation Summary
Figure 4-11 shows the three possible cache line states and possible processor-initiated
transitions for memory configured as copyback. Transitions are labeled with a capital letter
indicating the previous state and a number indicating the specific case listed in Table 4-11.
Figure 4-11. Cache Line State Diagram—Copyback Mode
Figure 4-12 shows the two possible states for a cache line in write-through mode.
Figure 4-12. Cache Line State Diagram—Write-Through Mode
Table 4-6 describes cache line transitions and the accesses that cause them.
Invalid
CD1—CPU
CI3—CPU
Valid
V = 1
Modified
read miss
write miss
CI5—CINVA
CI6—CPUSHL & DPI
CI7—CPUSHL & DPI
CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL & DPI
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
CD5—CINVA
CD6—CPUSHL & DPI
CV3—CPU write miss
CV4—CPU write hit
CI1—CPU read miss
CV5—CINVA
CV6—CPUSHL & DPI
V = 0
M = 0
V = 1
M = 1
CD7—CPUSHL
& DPI
WI1—CPU read miss
Invalid Valid
WI3—CPU write miss
WI5—CINVA
WI6—CPUSHL & DPI
WI7—CPUSHL & DPI
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DPI
WV5—CINVA
WV6—CPUSHL & DPI
V = 0 V = 1
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