Datasheet

5-6 MCF5307 User’s Manual
Programming Model
programming model by executing the WDEBUG instruction. Thus, the breakpoint
hardware in the debug module can be accessed by the external development system using
the debug serial interface or by the operating system running on the processor core.
Software is responsible for guaranteeing that accesses to these resources are serialized and
logically consistent. Hardware provides a locking mechanism in the CSR to allow the
external development system to disable any attempted writes by the processor to the
breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the
MCF5307 is using the WDEBUG instruction to access debug module registers or the
resulting behavior is undefined.
These registers, shown in Figure 5-4, are treated as 32-bit quantities, regardless of the
number of implemented bits.
Figure 5-4. Debug Programming Model
These registers are accessed through the BDM port by new BDM commands, WDMREG and
RDMREG, described in Section 5.5.3.3, “Command Set Descriptions.” These commands
contain a 5-bit field, DRc, that specifies the register, as shown in Table 5-3.
PC breakpoint mask register
PC breakpoint register
Data breakpoint register
Data breakpoint mask register
Trigger definition register
Configuration/status register
BDM address attribute register
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
All debug control registers are writable from the external development system or the CPU via the
WDEBUG instruction.
CSR is write-only from the programming model. It can be read or written through the BDM port using the
RDMREG and WDMREG commands.
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
31 15 7 0
31 15 7 0
31 15 0
31 15 0
31 15 0
31 15 0
31 15 0
31 15 0
AATR
ABLR
ABHR
BAAR
CSR
DBR
DBMR
PBR
PBMR
TDR
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