Datasheet

Chapter 5. Debug Support 5-7
Programming Model
NOTE:
Debug control registers can be written by the external
development system or the CPU through the WDEBUG
instruction.
CSR is write-only from the programming model. It can be read
or written through the BDM port using the
RDMREG and
WDMREG commands.
5.4.1 Address Attribute Trigger Register (AATR)
The address attribute trigger register (AATR) defines address attributes and a mask to be
matched in the trigger. The register value is compared with address attribute signals from
the processor’s local high-speed bus, as defined by the setting of the trigger definition
register (TDR).
Table 5-4 describes AATR fields
.
Table 5-3. BDM/Breakpoint Registers
DRc[4–0] Register Name Abbreviation Initial State Page
0x00 Configuration/status register CSR 0x0010_0000 p. 5-10
0x01–0x04 Reserved — — —
0x05 BDM address attribute register BAAR 0x0000_0005 p. 5-9
0x06 Address attribute trigger register AATR 0x0000_0005 p. 5-7
0x07 Trigger definition register TDR 0x0000_0000 p. 5-14
0x08 Program counter breakpoint register PBR — p. 5-13
0x09 Program counter breakpoint mask register PBMR — p. 5-13
0x0A–0x0B Reserved — — —
0x0C Address breakpoint high register ABHR — p. 5-8
0x0D Address breakpoint low register ABLR — p. 5-8
0x0E Data breakpoint register DBR — p. 5-12
0x0F Data breakpoint mask register DBMR — p. 5-12
1514131211109876543210
Field RM SZM TTM TMM R SZ TT TM
Reset 0000_0000_0000_0101
R/W Write only. AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG
instruction and through the BDM port using the
WDMREG command.
DRc[4–0] 0x06
Figure 5-5. Address Attribute Trigger Register (AATR)
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