Datasheet

5-10 MCF5307 User’s Manual
Programming Model
5.4.4 Configuration/Status Register (CSR)
The configuration/status register (CSR) defines the debug configuration for the processor
and memory subsystem and contains status information from the breakpoint logic.
Table 5-8 describes CSR fields.
Table 5-7. BAAR Field Descriptions
Bits Name Description
7 R Read/write
0 Write
1 Read
6–5 SZ Size
00 Longword
01 Byte
10 Word
11 Reserved
4–3 TT Transfer type. See the TT definition in Table 5-4.
2–0 TM Transfer modifier. See the TM definition in Table 5-4.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field BSTAT FOF TRG HALT BKPT HRL — BKD — IPW
Reset 0000 0 0 0 0 0001 — — — 0
R/W
1
R RRRR R ———R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field MAP TRC EMU DDC UHE BTB —
2
NPL IPI SSM —
Reset 0 0 0 00 0 00 0 0 — 0 —
R/W R/W R/W R/W R/W R/W R/W R R/W — R/W —
DRc[4–0] 0x00
1
CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR
is accessible in supervisor mode as debug control register 0x00 using the WDEBUG instruction and through
the BDM port using the
RDMREG and WDMREG commands.
2
Bit 7 is reserved for Motorola use and must be written as a zero.
Figure 5-8. Configuration/Status Register (CSR)
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