Datasheet

Chapter 5. Debug Support 5-13
Programming Model
Table 5-9 describes DBR fields.
Table 5-10 describes DBMR fields.
The DBR supports both aligned and misaligned references. Table 5-11 shows relationships
between processor address, access size, and location within the 32-bit data bus.
5.4.6 Program Counter Breakpoint/Mask Registers
(PBR, PBMR)
The PC breakpoint register (PBR) defines an instruction address for use as part of the
trigger. This register’s contents are compared with the processor’s program counter register
when TDR is configured appropriately. PBR bits are masked by clearing corresponding
PBMR bits. Results are compared with the processor’s program counter register, as defined
in TDR. Figure 5-10 shows the PC breakpoint register.
Table 5-9. DBR Field Descriptions
Bits Name Description
31–0 Data Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Table 5-10. DBMR Field Descriptions
Bits Name Description
31–0 Mask Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows
the corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus.
Setting a DBMR bit causes that bit to be ignored.
Table 5-11. Access Size and Operand Data Location
A[1:0] Access Size Operand Location
00 Byte D[31:24]
01 Byte D[23:16]
10 Byte D[15:8]
11 Byte D[7:0]
0x Word D[31:16]
1x Word D[15:0]
xx Longword D[31:0]
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