Datasheet

5-14 MCF5307 User’s Manual
Programming Model
Table 5-12 describes PBR fields.
Figure 5-11 shows PBMR.
Table 5-13 describes PBMR fields.
5.4.7 Trigger Definition Register (TDR)
The TDR, shown in Table 5-12, configures the operation of the hardware breakpoint logic
that corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers
within the debug module. The TDR controls the actions taken under the defined conditions.
Breakpoint logic may be configured as a one- or two-level trigger. TDR[31–16] define the
second-level trigger and bits 15–0 define the first-level trigger.
31 10
Field Program Counter
Reset —
R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through
the BDM port using the
RDMREG and WDMREG commands using values shown in Section 5.5.3.3, “Command
Set Descriptions.”
DRc[4–0] 0x08
Figure 5-10. Program Counter Breakpoint Register (PBR)
Table 5-12. PBR Field Descriptions
Bits Name Description
31–0 Address PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
31 0
Field Mask
Reset —
R/W Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
instruction and via the BDM port using the wdmreg command.
DRc[4–0] 0x09
Figure 5-11. Program Counter Breakpoint Mask Register (PBMR)
Table 5-13. PBMR Field Descriptions
Bits Name Description
31–0 Mask PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to
the appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
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