Datasheet

xvi
MCF5307 User’s Manual
CONTENTS
Paragraph
Number
Title
Page
Number
17.5.5.3 D[6:5]—Port Size Configuration (PS_CONFIG[1:0])........................... 17-14
17.5.6 D4—Address Configuration (ADDR_CONFIG)....................................... 17-14
17.5.7 D[3:2]—Frequency Control PLL (FREQ[1:0] ..........................................) 17-15
17.5.8 D[1:0]—Divide Control PCLK to BCLKO (DIVIDE[1:0])....................... 17-15
17.6 Chip-Select Module Signals ........................................................................... 17-15
17.6.1 Chip-Select (CS[7:0]) ................................................................................. 17-16
17.6.2 Byte Enables/Byte Write Enables (BE[3:0]/BWE[3:0]) ............................ 17-16
17.6.3 Output Enable (OE) .................................................................................... 17-16
17.7 DRAM Controller Signals .............................................................................. 17-16
17.7.1 Row Address Strobes (RAS[1:0])............................................................... 17-16
17.7.2 Column Address Strobes (CAS[3:0]) ......................................................... 17-16
17.7.3 DRAM Write (DRAMW)........................................................................... 17-17
17.7.4 Synchronous DRAM Column Address Strobe (SCAS) ............................. 17-17
17.7.5 Synchronous DRAM Row Address Strobe (SRAS)................................... 17-17
17.7.6 Synchronous DRAM Clock Enable (SCKE).............................................. 17-17
17.7.7 Synchronous Edge Select (EDGESEL)...................................................... 17-17
17.8 DMA Controller Module Signals.................................................................... 17-17
17.8.1 DMA Request (DREQ[1:0]/PP[6:5]).......................................................... 17-18
17.9 Serial Module Signals..................................................................................... 17-18
17.9.1 Transmitter Serial Data Output (TxD)........................................................ 17-18
17.9.2 Receiver Serial Data Input (RxD)............................................................... 17-18
17.9.3 Clear to Send (CTS).................................................................................... 17-18
17.9.4 Request to Send (RTS) ............................................................................... 17-18
17.10 Timer Module Signals..................................................................................... 17-18
17.10.1 Timer Inputs (TIN[1:0]).............................................................................. 17-19
17.10.2 Timer Outputs (TOUT1, TOUT0).............................................................. 17-19
17.11 Parallel I/O Port (PP[15:0]) ............................................................................ 17-19
17.12 I2C Module Signals ........................................................................................ 17-19
17.12.1 I2C Serial Clock (SCL)............................................................................... 17-19
17.12.2 I2C Serial Data (SDA)................................................................................ 17-19
17.13 Debug and Test Signals .................................................................................. 17-20
17.13.1 Test Mode (MTMOD[3:0]) ........................................................................ 17-20
17.13.2 High Impedance (HIZ
)................................................................................ 17-20
17.13.3 Processor Clock Output (PSTCLK)............................................................ 17-20
17.13.4 Debug Data (DDATA[3:0])........................................................................ 17-20
17.13.5 Processor Status (PST[3:0])........................................................................ 17-20
17.14 Debug Module/JTAG Signals......................................................................... 17-21
17.14.1 Test Reset/Development Serial Clock (TRST
/DSCLK) ............................ 17-21
17.14.2 Test Mode Select/Breakpoint (TMS/BKPT
) .............................................. 17-22
17.14.3 Test Data Input/Development Serial Input (TDI/DSI) ............................... 17-22
17.14.4 Test Data Output/Development Serial Output (TDO/DSO)....................... 17-22
17.14.5 Test Clock (TCK) ....................................................................................... 17-23
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...