Datasheet

5-42 MCF5307 User’s Manual
Motorola-Recommended BDM Pinout
• Read/write address and data registers
• Read/write control registers
For BDM commands that access memory, the debug module requests the processor’s local
bus. The processor responds by stalling the instruction fetch pipeline and waiting for
current bus activity to complete before freeing the local bus for the debug module to
perform its access. After the debug module bus cycle, the processor reclaims the bus.
Breakpoint registers must be carefully configured in a development system if the processor
is executing. The debug module contains no hardware interlocks, so TDR should be
disabled while breakpoint registers are loaded, after which TDR can be written to define the
exact trigger. This prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed
while the CPU is writing the debug’s registers (DSCLK must be inactive).
5.7 Motorola-Recommended BDM Pinout
The ColdFire BDM connector, Figure 5-44, is a 26-pin Berg connector arranged 2 x 13.
Figure 5-44. Recommended BDM Connector
5.8 Processor Status, DDATA Definition
This section specifies the ColdFire processor and debug module’s generation of the
processor status (PST) and debug data (DDATA) output on an instruction basis. In general,
the PST/DDATA output for an instruction is defined as follows:
PST = 0x1, {PST = [0x89B], DDATA= operand}
where the {...} definition is optional operand information defined by the setting of the CSR.
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
Developer reserved
1
GND
GND
RESET
Pad-Voltage
2
GND
PST2
PST0
DDATA2
DDATA0
Motorola reserved
GND
Core-Voltage
BKPT
DSCLK
Developer reserved
1
DSI
DSO
PST3
PST1
DDATA3
DDATA1
GND
Motorola reserved
CLK_CPU
TA
2
Supplied by target
1
Pins reserved for BDM developer use.
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eescale S
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