Datasheet

II-ii MCF5307 User’s Manual
includes a description of signals involved in DRAM operations. The remainder of
the chapter is divided between descriptions of asynchronous and synchronous
operations.
Suggested Reading
The following literature may be helpful with respect to the topics in Part II:
• The I
2
C Bus Specification, Version 2.1 (January 2000)
Acronyms and Abbreviations
Table II-i contains acronyms and abbreviations are used in Part II.
Table II-i. Acronyms and Abbreviated Terms
Term Meaning
ADC Analog-to-digital conversion
BDM Background debug mode
CODEC Code/decode
DAC Digital-to-analog conversion
DMA Direct memory access
DSP Digital signal processing
EDO Extended data output (DRAM)
FIFO First-in, first-out
GPIO
I
2
C Inter-integrated circuit
IEEE Institute for Electrical and Electronics Engineers
IPL Interrupt priority level
JEDEC Joint Electron Device Engineering Council
LIFO Last-in, first-out
LRU Least recently used
LSB Least-significant byte
lsb Least-significant bit
MBAR Memory base address register
MSB Most-significant byte
msb Most-significant bit
Mux Multiplex
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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