Datasheet

ILLUSTRATIONS
Figure
Number
Title
Page
Number
Illustrations xix
1-1 MCF5307 Block Diagram............................................................................................. 1-2
1-2 UART Module Block Diagram..................................................................................... 1-9
1-3 PLL Module................................................................................................................ 1-12
1-4 ColdFire MCF5307 Programming Model .................................................................. 1-13
2-1 ColdFire Enhanced Pipeline .......................................................................................2-23
2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................. 2-25
2-3 ColdFire Programming Model.................................................................................... 2-27
2-5 Status Register (SR).................................................................................................... 2-30
2-6 Vector Base Register (VBR)....................................................................................... 2-30
2-7 Organization of Integer Data Formats in Data Registers............................................ 2-32
2-8 Organization of Integer Data Formats in Address Registers ...................................... 2-32
2-9 Memory Operand Addressing..................................................................................... 2-33
2-10 Exception Stack Frame Form...................................................................................... 2-49
3-1 ColdFire MAC Multiplication and Accumulation........................................................ 3-2
3-2 MAC Programming Model........................................................................................... 3-2
4-1 SRAM Base Address Register (RAMBAR)................................................................. 4-3
4-2 Unified Cache Organization .........................................................................................4-7
4-3 Cache Organization and Line Format........................................................................... 4-8
4-4 Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern ....................... 4-10
4-5 Caching Operation ...................................................................................................... 4-11
4-6 Write-Miss in Copyback Mode................................................................................... 4-16
4-7 Cache Locking ............................................................................................................ 4-20
4-8 Cache Control Register (CACR) ................................................................................4-21
4-9 Access Control Register Format (ACRn) ................................................................... 4-23
4-10 A
n Format .................................................................................................................. 4-24
4-11 Cache Line State Diagram—Copyback Mode............................................................ 4-26
4-12 Cache Line State Diagram—Write-Through Mode.................................................... 4-26
5-1 Processor/Debug Module Interface............................................................................... 5-1
5-2 PSTCLK Timing........................................................................................................... 5-3
5-3 Example JMP Instruction Output on PST/DDATA...................................................... 5-5
5-4 Debug Programming Model ......................................................................................... 5-6
5-5 Address Attribute Trigger Register (AATR)................................................................ 5-7
5-6 Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9
5-7 BDM Address Attribute Register (BAAR)................................................................... 5-9
5-8 Configuration/Status Register (CSR).......................................................................... 5-10
5-9 Data Breakpoint/Mask Registers (DBR and DBMR)................................................. 5-12
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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