Datasheet

6-12 MCF5307 User’s Manual
Programming Model
6.2.10.1.1 Arbitration for Internally Generated Transfers (MPARK[PARK])
MPARK[PARK] prioritizes internal transfers, which can be initiated by the core and the
on-chip DMA module, which contains all four DMA channels. Priority among the four
DMA channels in the module is determined by the BWC bits in their respective DMA
control registers (see Chapter 12, “DMA Controller Module”).
The four arbitration schemes for internally generated transfers are described as follows:
• Round-robin scheme (PARK = 00)—Figure 6-10 shows round-robin arbitration
between the core and DMA module. Bus mastership alternates between the core and
DMA module.
Figure 6-10. Round Robin Arbitration (PARK = 00)
The DMA module presents only the highest-priority DMA request, and bus
mastership alternates between the core and DMA channel as long as both are
requesting bus mastership. Section 12.5.4.1, “External Request and Acknowledge
Operation,” includes a timing diagram showing a lower-priority DMA transfer.
When the processor is initialized, the core has first priority. If DMA channels 0 and
1 (both set to BWC = 010) assert an internal bus request during a core-generated bus
transfer, DMA channel 0 would gain bus mastership next. However, if the core
requests the bus during this DMA transfer, bus mastership returns to the core rather
than being granted to DMA channel 1.
3 SHOWDATA Enable internal register data bus to be driven on external bus. EARBCTRL must be set for
this function to work. Section 6.2.10.1.2, “Arbitration between Internal and External Masters
for Accessing Internal Resources,” describes the proper use of SHOWDATA.
0 Do not drive internal register data bus values to external bus.
1 Drive internal register data bus values to external bus.
2–1 — Reserved, should be cleared.
0 BCR24BIT Controls the BCR and address mapping for DMA. Allows the BCR to be used as a 24-bit
register. Chapter 12, “DMA Controller Module,” describes the BCRs.
0 DMA BCRs function as 16-bit counters.
1 DMA BCRs function as 24-bit counters.
Table 6-6. MPARK Field Descriptions (Continued)
Bits Name Description
CORE
Channel 0
Channel 1
Channel 2
Channel 3
DMA MODULE
Internal Bus Mastership
(Alternates between Core and DMA Module)
1st
2nd
3rd
4th
5th
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