Datasheet

Chapter 7. Phase-Locked Loop (PLL) 7-3
PLL Port List
7.2.4 PLL Control Register (PLLCR)
The PLL control register (PLLCR), Figure 7-2, provides control over the PLL.
Table 7-1 describes PLLCR bits.
7.3 PLL Port List
Table 7-2 describes PLL module inputs.
76543210
Field ENBSTOP PLLIPL —
Reset 0000_0000
R/W R/W
Address MBAR + 0x08
Figure 7-2. PLL Control Register (PLLCR)
Table 7-1. PLLCR Field Descriptions
Bit Name Description
7 ENBSTOP Enable CPU STOP instruction. Must be set for the ColdFire CPU STOP instruction to be
acknowledged. Cleared at reset and must be subsequently set for the processor to enter
low-power modes. Only clocks to the core are turned off because of the CPU STOP instruction.
Internal modules remain clocked and can generate interrupts to restart the ColdFire core.
0 Disable CPU STOP
1 Enable CPU STOP; STOP instruction turns off clocks to the ColdFire core.
6–4 PLLIPL PLL interrupt priority level to wake up from CPU STOP. Determines the minimum level an
interrupt (decoded as an interrupt priority level) must be to waken the PLL. The PLL then turns
clocks back on to the core processor and interrupt exception processing occurs.
000 Any interrupts can wake core
001 Interrupts 2–7
010 Interrupts 3–7
011 Interrupts 4–7
100 Interrupts 5–7
101 Interrupts 6–7
110 Interrupt 7 only
111 No interrupts can wake core. Any reset, including a watchdog reset, can wake the core.
No PLL phase lock time is required.
3–0 — Reserved, should be cleared.
Table 7-2. PLL Module Input SIgnals
SIgnal Description
CLKIN Input clock to the PLL. Input frequency must not be changed during operation. Changes are
recognized only at reset.
RSTI
Active-low asynchronous input that, when asserted, indicates PLL is to enter reset mode. As long as
RSTI
is asserted, the PLL is held in reset and does not begin to lock.
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