Datasheet

7-4 MCF5307 User’s Manual
Timing Relationships
Table 7-3 describes PLL module outputs.
7.4 Timing Relationships
The MCF5307 uses CLKIN and BCLKO, which is generated by the PLL and may be used
as the bus timing reference for external devices. The MCF5307 BCLKO frequency can be
1/2, 1/3, or 1/4 the processor clock. In this document, bus timings are referenced from
BCLKO. Furthermore, depending on the user configuration, the BCLKO-to-processor
clock ratio may differ from the CLKIN-to-processor clock ratio.
7.4.1 PCLK, PSTCLK, and BCLKO
Figure 7-3 shows the frequency relationships between PCLK, PSTCLK,CLKIN, and the
three possible versions of BCLKO. This figure does not show the skew between CLKIN
and PCLK, PSTCLK, and BCLKO. PSTCLK is equal to frequency of PCLK. Similarly, the
skew between PCLK and BCLKO is unspecified.
FREQ[1:0] Input bus indicating the CLKIN frequency range. FREQ[1:0] are multiplexed with D[3:2] and are
sampled while RSTI
is asserted. FREQ[1:0] must be correctly set for proper operation. These signals
do not affect CLKIN frequency but are required to set up the analog PLL to handle the input clock
frequency.
00 16.6
–27.999 MHz
01 28
–38.999 MHz
10 39
–45 MHz
11 Not used
DIVIDE[1:0] The MCF5307 samples clock ratio encodings on the lower data bits of the bus to determine the
CLKIN-to-processor clock ratio. D[1:0]/DIVIDE[1:0] support the divide-ratio combinations.
00 1/4
01 Not used
10 1/2
11 1/3
Table 7-3. PLL Module Output Signals
Output Description
BCLKO This bus clock output provides a divided version of the processor clock frequency, determined by
DIVIDE[1:0].
PSTCLK Provides a buffered processor status clock at 2X the CLKIN frequency. PSTCLK is a delayed version of
PCLK. See Section 7.4.1, “PCLK, PSTCLK, and BCLKO,” and Figure 7-1.
RST
O This output provides an external reset for peripheral devices.
Table 7-2. PLL Module Input SIgnals
SIgnal Description
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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