Datasheet

Chapter 7. Phase-Locked Loop (PLL) 7-5
Timing Relationships
Figure 7-3. CLKIN, PCLK, PSTCLK, and BCLKO Timing
7.4.2 RSTI Timing
Figure 7-4 shows PLL timing during reset. As shown, RSTI must be asserted for at least 80
CLKIN cycles to give the MCF5307 time to begin its initialization sequence. At this time,
the configuration pins should be asserted (D[3:2] for FREQ[1:0] and D[1:0] for
DIVIDE[1:0]), meeting the minimum setup and hold times to RSTI
given in Chapter 20,
“Electrical Specifications.”
On the rising edge of BCLKO before the rising edge of RSTI
, the data on D[7:0] is latched
and the PLL begins ramping to its final operating frequency. During this ramp and lock
time, BCLKO and PSTCLK are held low. The PLL locks in about 2.2 mS with a 45-MHz
CLKIN, at which time BCLKOand PSTCLK begin normal operation in the specified mode.
The PLL requires 100,000 CLKIN cycles to guarantee PLL lock. To allow for reset of
external peripherals requiring a clock source, RST
O remains asserted for a number of
BCLKO cycles, as shown in Figure 7-4.
PCLK
BCLKO (/2)
BCLKO (/3)
BCLKO (/4)
CLKIN
PSTCLK
NOTE: The clock signals are shown with edges aligned to show frequency relationships only.
Actual signal edges have some skew between them.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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