Datasheet

8-6 MCF5307 User’s Manual
Programming Model
8.5 Programming Model
Table 8-1 lists the configuration registers used in the I
2
C interface.
NOTE:
External masters cannot access the MCF5307’s on-chip
memories or MBAR, but can access any I
2
C module register.
8.5.1 I
2
C Address Register (IADR)
The IADR holds the address the I
2
C responds to when addressed as a slave. Note that it is
not the address sent on the bus during the address transfer.
Table 8-2 describes IADR fields.
Table 8-1. I
2
C Interface Memory Map
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
0x280 I
2
C address register (IADR) [p. 8-6] Reserved
0x284 I
2
C frequency divider register (IFDR) [p. 8-7] Reserved
0x288 I
2
C control register (I2CR) [p. 8-8] Reserved
0x28C I
2
C status register (I2SR) [p. 8-9] Reserved
0x290 I
2
C data I/O register (I2DR) [p. 8-10] Reserved
76543210
Field ADR —
Reset 0000_0000
R/W Read/Write
Address MBAR + 0x280
Figure 8-5. I
2
C Address Register (IADR)
Table 8-2. I
2
C Address Register Field Descriptions
Bits Name Description
7–1 ADR Slave address. Contains the specific slave address to be used by the I
2
C module. Slave mode is
the default I
2
C mode for an address match on the bus.
0 — Reserved, should be cleared.
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eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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