Datasheet

8-10 MCF5307 User’s Manual
I
2
C Programming Examples
8.5.5 I
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C Data I/O Register (I2DR)
In master-receive mode, reading the I2DR, Figure 8-9, allows a read to occur and initiates
next byte data receiving. In slave mode, the same function is available after it is addressed.
8.6 I
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C Programming Examples
The following examples show programming for initialization, signalling START,
post-transfer software response, signalling STOP, and generating a repeated START.
8.6.1 Initialization Sequence
Before the interface can transfer serial data, registers must be initialized, as follows:
1. Set IFDR[IC] to obtain SCL frequency from the system bus clock. See
Section 8.5.2, “I2C Frequency Divider Register (IFDR).”
2. Update the IADR to define its slave address.
3. Set I2CR[IEN] to enable the I
2
C bus interface system.
4. Modify the I2CR to select master/slave mode, transmit/receive mode, and
interrupt-enable or not.
NOTE:
If IBSR[IBB] when the I
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C bus module is enabled, execute the
following code sequence before proceeding with normal
initialization code. This issues a STOP command to the slave
device, placing it in idle state as if it were just power-cycled on.
I2CR = 0x0
I2CR = 0xA
dummy read of I2DR
IBSR = 0x0
I2CR = 0x0
8.6.2 Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting
the master transmitter mode. On a multiple-master bus system, IBSR[IBB] must be tested
to determine whether the serial bus is free. If the bus is free (IBB = 0), the START signal
76543210
Field D
Reset 0000_0000
R/W Read/Write
Address MBAR + 0x290
Figure 8-9. I
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C Data I/O Register (I2DR)
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eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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