Datasheet

10-4 MCF5307 User’s Manual
Chip-Select Operation
10.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See
Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7).” Figure 10-1 shows
the correspondence between data byte lanes and the external chip-select memory. Note that
all lanes are driven, although unused lines are undefined.
Figure 10-1. Connections for External Memory Port Sizes
10.3.1.2 Global Chip-Select Operation
CS0, the global (boot) chip select, allows address decoding for boot ROM before system
initialization. Its operation differs from other external chip-select outputs after system reset.
After system reset, CS0
is asserted for every external access. No other chip-select can be
used until the valid bit, CSMR0[V], is set, at which point CS0
functions as configured and
CS
[7:1] can be used. At reset, the port size and automatic acknowledge functions of the
global chip-select are determined by the logic levels of the inputs on D[7:5]. Table 10-4 and
Table 10-5list the various reset encodings for the configuration signals multiplexed with
D[7:5].
Provided the required address range is in the chip-select address register (CSAR0), CS0
can
Table 10-4. D7/AA, Automatic Acknowledge of Boot CS0
D7/AA Boot CS0 AA Configuration at Reset
0 Disabled
1 Enable with 15 wait states
Table 10-5. D[6:5]/PS[1:0], Port Size of Boot CS0
D[6:5]/PS[1:0] Boot CS0 Port Size at Reset
00 32-bit port
01 8-bit port
1x 16-bit port
Byte 0
8-bit port
16-bit port
32-bit port
Byte 1
Byte 2
Byte 3
Byte 0 Byte 1
Byte 2 Byte 3
Byte 0 Byte 1 Byte 2 Byte 3
D[31:24] D[23:16] D[15:8] D[7:0]
External
memory
memory
memory
data bus
BE0
BE1 BE2 BE3
Driven, undefined
Driven, undefined
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eescale S
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