Datasheet

10-6 MCF5307 User’s Manual
Chip-Select Registers
NOTE:
External masters cannot access MCF5307 on-chip memories or
MBAR, but can access any of the chip-select module registers.
10.4.1 Chip-Select Module Registers
The chip-select module is programmed through the chip select address registers
(CSAR0–CSAR7), chip select mask registers (CSMR0–CSMR7), and the chip select
control registers (CSCR0–CSCR7).
10.4.1.1 Chip-Select Address Registers (CSAR0–CSAR7)
Chip select address registers, Figure 10-2, specify the chip select base addresses.
Table 10-7 describes CSAR[BA].
10.4.1.2 Chip-Select Mask Registers (CSMR0–CSMR7)
The chip select mask registers, Figure 10-3, are used to specify the address mask and
allowable access types for the respective chip selects.
0x0D8 Chip-select mask register—bank 7 (CSMR7) [p. 10-6]
0x0DC Reserved
1
Chip-select control register—bank 7
(CSCR7) [p. 10-8]
1
Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to
these reserved address spaces and reserved register bits have no effect.
15 0
Field BA
Reset Uninitialized
R/W R/W
Addr 0x080 (CSAR0); 0x08C (CSAR1); 0x098 (CSAR2); 0x0A4 (CSAR3);
0x0B0 (CSAR4); 0x0BC (CSAR5); 0x0C8 (CSAR6); 0x0D4 (CSAR7)
Figure 10-2. Chip Select Address Registers (CSAR0–CSAR7)
Table 10-7. CSARn Field Description
Bits Name Description
15–0 BA Base address. Defines the base address for memory dedicated to chip select CS
[7:0]. BA is compared
to bits 31–16 on the internal address bus to determine if chip-select memory is being accessed.
Table 10-6. Chip-Select Registers (Continued)
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
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eescale S
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