Datasheet

10-8 MCF5307 User’s Manual
Chip-Select Registers
10.4.1.3 Chip-Select Control Registers (CSCR0–CSCR7)
Each chip-select control register, Figure 10-4, controls the auto acknowledge, external
master support, port size, burst capability, and activation of each chip select. Note that to
support the global chip select, CS0
, the CSCR0 reset values differ from the other CSCRs.
CS0
allows address decoding for boot ROM before system initialization.
Figure 10-4. Chip-Select Control Registers (CSCR0–CSCR7)
Table 10-9 describes CSCRn fields.
151413 1098765 4 3 2 0
Field — WS — AA PS1 PS0 BEM BSTR BSTW —
Reset: CSCR0 — 11_11 — D7 D6 D5 ——
Reset: Other CSCRs Unitialized
R/W R/W
Address 0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3);
0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6); 0x0DE (CSCR7)
Table 10-9. CSCRn Field Descriptions
Bits Name Description
15–14 — Reserved, should be cleared.
13–10 WS Wait states. The number of wait states inserted before an internal transfer acknowledge is generated
(WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, T
A must be asserted by
the external system regardless of the number of wait states generated. In that case, the external
transfer acknowledge ends the cycle. An external T
A supersedes the generation of an internal TA.
9 — Reserved, should be cleared.
8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for
accesses specified by the chip-select address.
0 No internal T
A is asserted. Cycle is terminated externally.
1 Internal T
A is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the
external system asserts an external T
A before the wait-state countdown asserts the internal TA, the
cycle is terminated. Burst cycles increment the address bus between each internal termination.
7–6 PS Port size. Specifies the width of the data associated with each chip select. It determines where data
is driven during write cycles and where data is sampled during read cycles. See Section 10.3.1.1,
“8-, 16-, and 32-Bit Port Sizing.”
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
5 BEM Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must
be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the
appropriate mode of byte enable in support of these SRAMs.
0 Neither BE
nor BWE is asserted for read. BWE is generated for data write only.
1BE
is asserted for read; BWE is asserted for write.
4 BSTR Burst read enable. Specifies whether burst reads are used for memory associated with each CS
n.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For
example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and
16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
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eescale S
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or
, I
Freescale Semiconductor, Inc.
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