Datasheet

11-34 MCF5307 User’s Manual
SDRAM Example
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next
access to the SDRAM address space generates the
MRS command to that SDRAM. The
address of the access should be selected to place the correct mode information on the
SDRAM address pins. The address is not multiplexed for the
MRS command. The MRS
access can be a read or write. The important thing is that the address output of that access
needs the correct mode programming information on the correct address bits.
Figure 11-24 shows the
MRS command, which occurs in the first clock of the bus cycle.
Figure 11-24. Mode Register Set (MRS) Command
11.5 SDRAM Example
This example interfaces a 2M x 32-bit x 4 bank SDRAM component to a MCF5307
operating at 40 MHz. Table 11-32 lists design specifications for this example.
Table 11-32. SDRAM Example Specifications
Parameter Specification
Speed grade (-8E) 40 MHz (25-nS period)
10 rows, 8 columns
Two bank-select lines to access four internal banks
ACTV-to-read/write delay (t
RCD
) 20 nS (min.)
Period between auto refresh and
ACTV command (t
RC
) 70 nS
ACTV command to precharge command (t
RAS
) 48 nS (min.)
Precharge command to
ACTV command (t
RP
) 20 nS (min.)
Last data input to
PALL command (t
RWL
) 1 bus clock (25 nS)
Auto refresh period for 4096 rows (t
REF
) 64 mS
A[31:0]
SRAS
, SCAS
DRAMW
D[31:0]
MRS
RAS[1] or [0]
BCLKO
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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