Datasheet

12-2 MCF5307 User’s Manual
DMA Signal Description
12.1.1 DMA Module Features
The DMA controller module features are as follows:
• Four fully independent, programmable DMA controller channels/bus modules
• Auto-alignment feature for source or destination accesses
• Dual- and single-address transfers
• Two external request pins (DREQ
[1:0]) provided for channels 1 and 0
• Channel arbitration on transfer boundaries
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode and cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Data transfer can occur in as few as two clocks
12.2 DMA Signal Description
Table 12-1 briefly describes the DMA module signals that provide handshake control for
either a source or destination external device.
Table 12-1. DMA Signals
Signal I/O Description
DREQ
[1:0]/
PP[6:5]
I External DMA request. DREQ[1:0] can serve as the DMA request inputs or as two parallel port
bits. They are programmable individually through the PAR. A peripheral device asserts these
inputs to request an operand transfer between it and memory.
DREQ
signals are asserted to initiate DMA accesses in the respective channels. The system
should drive unused DREQ
signals to logic high. Although each channel has an individual
DREQ
signal, in the MCF5307 only channels 0 and 1 connect to external DREQ pins.DREQ
signals for channels 2 and 3 are connected to the UART0 and UART1 bus interrupt signals.
TT[1:0]/
PP[1:0]
O Transfer type. A DMA access is indicated by the transfer type pins, TT[1:0] = 01. The transfer
modifier, TM[2:0] configurations shown below are meaningful only if TT[1:0] = 01, indicating an
external master or DMA access.
TM[2:0]
/PP[4:2]
O Multiplexed transfer attribute pins. The encodings below are valid when TT[1:0] = 01 and
internal DMA channels are driving the bus. DMA transfer information on TM[2:1] can be
provided on every DMA transfer or only on the last transfer by programming DCR[AT].
TM[2:1]Encoding
00 DMA acknowledge information not provided
01 DMA transfer, channel 0
10 DMA transfer, channel 1
11 Reserved
TM0 Encoding for DMA as master (TT = 01)
0 Single-address access negated
1 Single-address access
For TT[1:0] = 01, the TM0 encoding is independent of TM[2:1]. If DCR[SAA] is set, TM0
designates a single-address DMA access.
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eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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