Datasheet

12-6 MCF5307 User’s Manual
DMA Controller Module Programming Model
NOTE:
External masters cannot access MCF5307 on-chip memories or
MBAR, but they can access DMA module registers.
12.4.1 Source Address Registers (SAR0–SAR3)
SARn, Figure 12-4, contains the address from which the DMA controller requests data. In
single-address mode, SARn provides the address regardless of the direction.
NOTE:
SAR/DAR address ranges cannot be programmed to on-chip
SRAM because it cannot be accessed by on-chip DMA.
3 0x3C0 Source address register 3 (SAR3) [p. 12-6]
0x3C4 Destination address register 3 (DAR3) [p. 12-7]
0x3C8 DMA control register 3 (DCR3) [p. 12-8]
0x3CC Byte count register 3 (BCR24BIT = 0)
1
Reserved
0x3CC Reserved Byte count register 3 (BCR24BIT = 1)
1
(BCR3) [p. 12-7]
0x3D0 DMA status register 3
(DSR3) [p. 12-10]
Reserved
0x3D4 DMA interrupt vector
register 3 (DIVR3)
[p. 12-11]
Reserved
1
On the original MCF5307 mask set (H55J), the BCR of the DMA channels can accommodate only 16 bits.
However, because the revised MCF5307 supports a 24-bit byte count range, the position of the BCR in the
memory map depends on whether a 16- or 24-bit byte counter is selected. The 24-bit byte count can be
selected by setting BCR24BIT = 1, making DCR[AT] available. The AT bit selects whether DMA channels
assert acknowledge during the entire transfer or only at the final transfer of a DMA transaction.
New applications should take advantage of the full range of the 24-bit byte counter, including the AT bit. The
16-bit byte count option (BCR24BIT = 0) retains compatibility with older MCF5307 revisions.
31 0
Field SAR
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W R/W
Address MBAR + 0x300, 0x340, 0x380, 0x3C0
Figure 12-4. Source Address Registers (SARn)
Table 12-2. Memory Map for DMA Controller Module Registers (Continued)
DMA
Channel
MBAR
Offset
[31:24] [23:16] [15:8] [7:0]
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...