Datasheet

Chapter 12. DMA Controller Module 12-7
DMA Controller Module Programming Model
12.4.2 Destination Address Registers (DAR0–DAR3)
For dual-address transfers only, DARn, Figure 12-5, holds the address to which the DMA
controller sends data.
Figure 12-5. Destination Address Registers (DARn)
NOTE:
On-chip DMAs do not maintain coherency with MCF5307
caches and so must not transfer data to cacheable memory.
12.4.3 Byte Count Registers (BCR0–BCR3)
BCRn, Figure 12-6 and Figure 12-7, holds the number of bytes yet to be transferred for a
given block.The offset within the memory map is based on the value of
MPARK[BCR24BIT]. BCRn decrements on the successful completion of the address
transfer of either a write transfer in dual-address mode or any transfer in single-address
mode. BCRn decrements by 1, 2, 4, or 16 for byte, word, longword, or line accesses,
respectively.
Figure 12-6 shows BCR for BCR24BIT = 1.
Figure 12-6. Byte Count Registers (BCRn)—BCR24BIT = 1
Figure 12-7 shows BCR for BCR24BIT = 0.
31 0
Field DAR
Reset 0000_0000_0000_0000_0000_0000_0000_0000
R/W R/W
Address MBAR + 304, 0x344, 0x384, 0x3C4
31 24 23 0
Field — BCR
Reset — 0000_0000_0000_0000_0000_0000
R/W R/W
Address MBAR + 0x30C, 0x34C, 0x38C, 0x3AC
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