Datasheet

Chapter 12. DMA Controller Module 12-9
DMA Controller Module Programming Model
29 CS Cycle steal.
0 DMA continuously makes read/write transfers until the BCR decrements to 0.
1 Forces a single read/write transfer per request. The request may be internal by setting the START
bit, or external by asserting DREQ
.
28 AA Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is,
transfers are optimized based on the address and size. See Section 12.5.4.2, “Auto-Alignment.”
0 Auto-align disabled
1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned;
otherwise, destination accesses are auto-aligned. Source alignment takes precedence over
destination alignment. If auto-alignment is enabled, the appropriate address register increments,
regardless of DINC or SINC.
27–25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches
a multiple of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is
001 (512 bytes or value of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of
0x2000, 0x1E00, 0x1C00, 0x1A00, 0x1800, 0x1600, 0x1400, 0x1200, 0x1000, 0x0E00, 0x0C00,
0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200. If BCR24BIT is 0, BWC is 110, and BCR is 33000,
the bus is released after 232 bytes because the BCR is at 32768, a multiple of 16384.
BWC BCR24BIT = 0 BCR24BIT = 1
000 DMA has priority. It does not negate its request until its transfer completes.
001 512 16384
010 1024 32768
011 2048 65536
100 4096 131072
101 8192 262144
110 16384 524288
111 32768 1048576
24 SAA Single-address access. Determines whether the DMA channel is in dual- or single-address mode
0 Dual-address mode.
1 Single-address mode. The DMA provides an address from the SAR and directional control, bit
S_RW, to allow two peripherals (one might be memory) to exchange data within a single access.
Data is not stored by the DMA.
23 S_RW Single-address access read/write value. Valid only if SAA = 1. Specifies the value of the read signal
during single-address accesses. This provides directional control to the bus controller.
0 Forces the read signal to 0.
1 Forces the read signal to 1.
22 SINC Source increment. Controls whether a source address increments after each successful transfer.
0 No change to SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.
21–20 SSIZE Source size. Determines the data size of the source bus cycle for the DMA control module.
00 Longword
01 Byte
10 Word
11 Line
19 DINC Destination increment. Controls whether a destination address increments after each successful
transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.
18–17 DSIZE Destination size. Determines the data size of the destination bus cycle for the DMA controller.
00 Longword
01 Byte
10 Word
11 Line
Table 12-3. DCRn Field Descriptions (Continued)
Bits Name Description
Fr
eescale S
emiconduct
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, I
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