Datasheet

Tables xxix
TABLES
Table
Number
Title
Page
Number
17-10 Data Pin Configuration ............................................................................................. 17-12
17-11 D7 Selection of CS0 Automatic Acknowledge ........................................................17-13
17-12 D6 and D5 Selection of CS0 Port Size ..................................................................... 17-13
17-13 D4/ADDR_CONFIG, Address Pin Assignment....................................................... 17-13
17-14 CLKIN Frequency ....................................................................................................17-13
17-15 BCLKO/PSTCLK Divide Ratios.............................................................................. 17-14
17-16 Processor Status Signal Encodings........................................................................... 17-19
18-1 ColdFire Bus Signal Summary ................................................................................... 18-1
18-2 Bus Cycle Size Encoding............................................................................................ 18-3
18-3 Accesses by Matches in CSCRs and DACRs............................................................. 18-5
18-4 Bus Cycle States ......................................................................................................... 18-6
18-5 Allowable Line Access Patterns ............................................................................... 18-12
18-6 MCF5307 Arbitration Protocol States ...................................................................... 18-20
18-7 ColdFire Bus Arbitration Signal Summary............................................................... 18-21
18-8 Cycles for Basic No-Wait-State External Master Access......................................... 18-23
18-9 Cycles for External Master Burst Line Access to 32-Bit Port.................................. 18-24
18-10 MCF5307 Two-Wire Bus Arbitration Protocol Transition Conditions.................... 18-28
18-11 Three-Wire Bus Arbitration Protocol Transition Conditions ................................... 18-32
18-12 Data Pin Configuration ............................................................................................. 18-35
19-1 JTAG Pin Descriptions ............................................................................................... 19-3
19-2 JTAG Instructions....................................................................................................... 19-5
19-3 IDCODE Bit Assignments.......................................................................................... 19-6
19-4 Boundary-Scan Bit Definitions................................................................................... 19-7
20-1 Absolute Maximum Ratings ....................................................................................... 20-1
20-2 Operating Temperatures.............................................................................................. 20-1
20-3 DC Electrical Specifications....................................................................................... 20-2
20-4 Clock Timing Specification........................................................................................ 20-2
20-5 Input AC Timing Specification................................................................................... 20-3
20-6 Output AC Timing Specification................................................................................ 20-4
20-7 Reset Timing Specification....................................................................................... 20-12
20-8 Debug AC Timing Specification ..............................................................................20-12
20-9 Timer Module AC Timing Specification.................................................................. 20-14
20-10 I
2
C Input Timing Specifications between SCL and SDA......................................... 20-15
20-11 I
2
C Output Timing Specifications between SCL and SDA...................................... 20-15
20-12 UART Module AC Timing Specifications ............................................................... 20-16
20-13 General-Purpose I/O Port AC Timing Specifications............................................... 20-18
20-14 DMA AC Timing Specifications .............................................................................. 20-19
20-15 IEEE 1149.1 (JTAG) AC Timing Specifications .....................................................20-20
A-1 SIM Registers............................................................................................................... A-1
A-2 Interrupt Controller Registers ...................................................................................... A-1
A-3 Chip-Select Registers................................................................................................... A-2
A-4 DRAM Controller Registers ........................................................................................ A-3
A-5 General-Purpose Timer Registers................................................................................ A-4
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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