Datasheet

Chapter 12. DMA Controller Module 12-15
DMA Controller Module Functional Description
Figure 12-11. DREQ Timing Constraints, Dual-Address DMA Transfer
Although Figure 12-11 does not show TM0 signaling a DMA acknowledgement, this signal
can provide an external request acknowledge response, as shown in subsequent diagrams.
To initiate a request, DREQ
need only be asserted long enough to be sampled on one rising
clock edge. However, note the following regarding the negation of DREQ
:
• In cycle-steal mode (DCR[CS] = 1), the read/write transaction is limited to a single
transfer. DREQ
must be negated appropriately to avoid generating another request.
— For dual-address transfers, DREQ
must be negated before TS is asserted for the
write portion, as shown in Figure 12-11, clock cycle 7.
— For single-address transfers, DREQ
must be negated before TS is asserted for the
transfer, as shown in Figure 12-13, clock cycle 4.
• In burst mode, (DCR[CS] = 0), multiple read/write transfers can occur on the bus as
programmed. DREQ
need not be negated until DSR[DONE] is set, indicating the
block transfer is complete. Another transfer cannot be initiated until the DMA
registers are reprogrammed.
Figure 12-12 shows a dual-address, peripheral-to-SDRAM DMA transfer. The DMA is not
parked on the bus, so the diagram shows how the CPU can generate multiple bus cycles
during DMA transfers. It also shows TM0 timing. The TT signals indicate whether the CPU
(0) or DMA (1) has bus mastership. TM2 indicates dual-address mode.
If DCR[AT] is 1, TM is asserted during the final transfer. If DCR[AT] is 0, TM asserts
during all DMA accesses.
DREQ0
TT1
TT0
TS
CS
TA
R/W
0
CLKIN
1234567891011
A[31:0]
Read Write
TM0
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eescale S
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