Datasheet

14-14 MCF5307 User’s Manual
Register Descriptions
14.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn)
The UDUn registers (formerly called UBG1n) holds the MSB, and the UDLn registers
(formerly UBG2n) hold the LSB of the preload value. UDUn and UDLn concatenate to
provide a divider to BCLKO for transmitter/receiver operation, as described in
Section 14.5.1.2.1, “BCLKO Baud Rates.”
NOTE:
The minimum value that can be loaded on the concatenation of
UDUn with UDLn is 0x0002. Both UDUn and UDLn are
write-only and cannot be read by the CPU.
Table 14-9. UISRn/UIMRn Field Descriptions
Bits Name Description
7 COS Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on CTS
and was programmed in UACRn[IEC] to cause an interrupt.
6–3 — Reserved, should be cleared.
2 DB Delta break.
0 No new break-change condition to report. Section 14.3.5, “UART Command Registers (UCRn),”
describes the
RESET BREAK-CHANGE INTERRUPT command.
1 The receiver detected the beginning or end of a received break.
1 FFULL/
RxRDY
RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if UMR1n[FFULL/RxRDY]
= 1. Duplicate of USRn[FFULL/RxRDY]. If FFULL is enabled for UART0 or UART1, DMA channels 2
or 3 are respectively interrupted when the FIFO is full.
0 TxRDY Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters
loaded into the transmitter holding register when TxRDY = 0 are not sent.
1 The transmitter holding register is empty and ready to be loaded with a character.
7 0
Field Divider MSB
Reset 0000_0000
R/W R/W
Address MBAR + 0x1D8 (UDU0), 0x218 (UDU1)
Figure 14-12. UART Divider Upper Register (UDUn)
7 0
Field Divider LSB
Reset 0000_0000
R/W R/W
Address MBAR + 0x1DC (UDL0), 0x21C (UDL1)
Figure 14-13. UART Divider Lower Register (UDLn)
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...