Datasheet

14-16 MCF5307 User’s Manual
UART Module Signal Definitions
Table 14-12 describes UOP1 fields.
14.4 UART Module Signal Definitions
Figure 14-17 shows both the external and internal signal groups.
Figure 14-17. UART Block Diagram Showing External and Internal Interface Signals
An internal interrupt request signal (IRQ) is provided to notify the interrupt controller of an
interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt
level of a UART module is programmed in the interrupt controller in the system integration
module (SIM). The UART can use the autovector for the programmed interrupt level or
supply the vector from the UIVRn when the UART interrupt is acknowledged.
7 10
Field — RTS
Reset 0000_0000
R/W Write only
Addr UART0: MBAR + 0x1F8 (UOP1), 0x1FC (UOP0); UART1 0x238 (UOP1), 0x23C (UOP0)
Figure 14-16. UART Output Port Command Register (UOP1/UOP0)
Table 14-12. UOP1/UOP0 Field Descriptions
Bits Name Description
7–1 — Reserved, should be cleared.
0 RTS Output port parallel output. Controls assertion (UOP1)/negation (UOP0) of RTS output.
0 Not affected.
1 Asserts R
TS (UOP1). Negates RTS (UOP0).
Internal
Four-Character
Receive Buffer
Two-Character
Transmit Buffer
Input Port
Output Port
Interface
UART Module
Address Bus
Control
CTS
RTS
RxD
TxD
Control
Logic
or
External Clock (TIN)
Internal Bus
Data
to CPU
IRQ
To Interrupt
Controller
(SIM)
External
Interface
Signals
BCLKO
Clock Source
Generator
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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